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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple aarch64 -run-pass=aarch64-prelegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s3---4name:            sextload_from_inreg5alignment:       46tracksRegLiveness: true7liveins:8  - { reg: '$x0' }9body:             |10  bb.1:11    liveins: $x012 13    ; CHECK-LABEL: name: sextload_from_inreg14    ; CHECK: liveins: $x015    ; CHECK-NEXT: {{  $}}16    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x017    ; CHECK-NEXT: [[SEXTLOAD:%[0-9]+]]:_(s16) = G_SEXTLOAD [[COPY]](p0) :: (load (s8), align 2)18    ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SEXTLOAD]](s16)19    ; CHECK-NEXT: $w0 = COPY [[ANYEXT]](s32)20    ; CHECK-NEXT: RET_ReallyLR implicit $w021    %0:_(p0) = COPY $x022    %1:_(s16) = G_LOAD %0(p0) :: (load (s16))23    %2:_(s16) = G_SEXT_INREG %1, 824    %3:_(s32) = G_ANYEXT %2(s16)25    $w0 = COPY %3(s32)26    RET_ReallyLR implicit $w027 28...29---30name:            sextload_from_inreg_across_store31alignment:       432tracksRegLiveness: true33liveins:34  - { reg: '$x0' }35body:             |36  bb.1:37    liveins: $x038    ; Check that the extend gets folded into the load, not the other way around, which39    ; could cause mem dependence violations.40    ; CHECK-LABEL: name: sextload_from_inreg_across_store41    ; CHECK: liveins: $x042    ; CHECK-NEXT: {{  $}}43    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x044    ; CHECK-NEXT: [[SEXTLOAD:%[0-9]+]]:_(s16) = G_SEXTLOAD [[COPY]](p0) :: (load (s8), align 2)45    ; CHECK-NEXT: G_STORE [[COPY]](p0), [[COPY]](p0) :: (store (p0))46    ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SEXTLOAD]](s16)47    ; CHECK-NEXT: $w0 = COPY [[ANYEXT]](s32)48    ; CHECK-NEXT: RET_ReallyLR implicit $w049    %0:_(p0) = COPY $x050    %1:_(s16) = G_LOAD %0(p0) :: (load (s16))51    G_STORE %0(p0), %0(p0) :: (store (p0))52    %2:_(s16) = G_SEXT_INREG %1, 853    %3:_(s32) = G_ANYEXT %2(s16)54    $w0 = COPY %3(s32)55    RET_ReallyLR implicit $w056 57...58---59name:            non_pow_2_inreg60alignment:       461tracksRegLiveness: true62liveins:63  - { reg: '$x0' }64body:             |65  bb.1:66    liveins: $x067 68    ; CHECK-LABEL: name: non_pow_2_inreg69    ; CHECK: liveins: $x070    ; CHECK-NEXT: {{  $}}71    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x072    ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load (s32))73    ; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[LOAD]], 2474    ; CHECK-NEXT: $w0 = COPY [[SEXT_INREG]](s32)75    ; CHECK-NEXT: RET_ReallyLR implicit $w076    %0:_(p0) = COPY $x077    %1:_(s32) = G_LOAD %0(p0) :: (load (s32))78    %2:_(s32) = G_SEXT_INREG %1, 2479    $w0 = COPY %2(s32)80    RET_ReallyLR implicit $w081 82...83---84name:            atomic85alignment:       486tracksRegLiveness: true87liveins:88  - { reg: '$x0' }89body:             |90  bb.1:91    liveins: $x092 93    ; CHECK-LABEL: name: atomic94    ; CHECK: liveins: $x095    ; CHECK-NEXT: {{  $}}96    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x097    ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s16) = G_LOAD [[COPY]](p0) :: (load acquire (s16))98    ; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s16) = G_SEXT_INREG [[LOAD]], 899    ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SEXT_INREG]](s16)100    ; CHECK-NEXT: $w0 = COPY [[ANYEXT]](s32)101    ; CHECK-NEXT: RET_ReallyLR implicit $w0102    %0:_(p0) = COPY $x0103    %1:_(s16) = G_LOAD %0(p0) :: (load acquire (s16))104    %2:_(s16) = G_SEXT_INREG %1, 8105    %3:_(s32) = G_ANYEXT %2(s16)106    $w0 = COPY %3(s32)107    RET_ReallyLR implicit $w0108 109...110---111name:            volatile112alignment:       4113tracksRegLiveness: true114liveins:115  - { reg: '$x0' }116body:             |117  bb.1:118    liveins: $x0119 120    ; CHECK-LABEL: name: volatile121    ; CHECK: liveins: $x0122    ; CHECK-NEXT: {{  $}}123    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0124    ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s16) = G_LOAD [[COPY]](p0) :: (volatile load (s16))125    ; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s16) = G_SEXT_INREG [[LOAD]], 8126    ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SEXT_INREG]](s16)127    ; CHECK-NEXT: $w0 = COPY [[ANYEXT]](s32)128    ; CHECK-NEXT: RET_ReallyLR implicit $w0129    %0:_(p0) = COPY $x0130    %1:_(s16) = G_LOAD %0(p0) :: (volatile load (s16))131    %2:_(s16) = G_SEXT_INREG %1, 8132    %3:_(s32) = G_ANYEXT %2(s16)133    $w0 = COPY %3(s32)134    RET_ReallyLR implicit $w0135 136...137