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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple aarch64 -run-pass=aarch64-prelegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s3 4---5name: shuffle_vector_undef_rhs6tracksRegLiveness: true7body: |8 bb.1:9 liveins: $d010 11 ; CHECK-LABEL: name: shuffle_vector_undef_rhs12 ; CHECK: liveins: $d013 ; CHECK-NEXT: {{ $}}14 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $d015 ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<2 x s32>) = G_IMPLICIT_DEF16 ; CHECK-NEXT: [[SHUF:%[0-9]+]]:_(<4 x s32>) = G_SHUFFLE_VECTOR [[COPY]](<2 x s32>), [[DEF]], shufflemask(0, undef, 1, undef)17 ; CHECK-NEXT: RET_ReallyLR implicit [[SHUF]](<4 x s32>)18 %0:_(<2 x s32>) = COPY $d019 %1:_(<2 x s32>) = G_IMPLICIT_DEF20 %2:_(<4 x s32>) = G_SHUFFLE_VECTOR %0(<2 x s32>), %1(<2 x s32>), shufflemask(0, 2, 1, 3)21 RET_ReallyLR implicit %222...23