216 lines · plain
1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -verify-machineinstrs -mtriple aarch64--- -run-pass=instruction-select -global-isel-abort=1 %s -o - | FileCheck %s3---4name: test_loop_phi_fpr_to_gpr5alignment: 46legalized: true7regBankSelected: true8selected: false9failedISel: false10tracksRegLiveness: true11liveins: []12machineFunctionInfo: {}13body: |14 ; CHECK-LABEL: name: test_loop_phi_fpr_to_gpr15 ; CHECK: bb.0:16 ; CHECK-NEXT: successors: %bb.1(0x80000000)17 ; CHECK-NEXT: {{ $}}18 ; CHECK-NEXT: [[DEF:%[0-9]+]]:gpr32 = IMPLICIT_DEF19 ; CHECK-NEXT: [[DEF1:%[0-9]+]]:gpr64common = IMPLICIT_DEF20 ; CHECK-NEXT: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 214328934421 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY [[MOVi32imm]]22 ; CHECK-NEXT: {{ $}}23 ; CHECK-NEXT: bb.1:24 ; CHECK-NEXT: successors: %bb.2(0x80000000)25 ; CHECK-NEXT: {{ $}}26 ; CHECK-NEXT: [[DEF2:%[0-9]+]]:gpr32 = IMPLICIT_DEF27 ; CHECK-NEXT: [[ANDSWri:%[0-9]+]]:gpr32 = ANDSWri [[DEF]], 0, implicit-def $nzcv28 ; CHECK-NEXT: [[CSELWr:%[0-9]+]]:gpr32 = CSELWr [[DEF2]], [[DEF2]], 1, implicit $nzcv29 ; CHECK-NEXT: {{ $}}30 ; CHECK-NEXT: bb.2:31 ; CHECK-NEXT: successors: %bb.2(0x80000000)32 ; CHECK-NEXT: {{ $}}33 ; CHECK-NEXT: [[PHI:%[0-9]+]]:gpr32 = PHI [[CSELWr]], %bb.1, %8, %bb.234 ; CHECK-NEXT: [[FCVTHSr:%[0-9]+]]:fpr16 = nofpexcept FCVTHSr [[COPY]], implicit $fpcr35 ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:fpr32 = SUBREG_TO_REG 0, [[FCVTHSr]], %subreg.hsub36 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32all = COPY [[SUBREG_TO_REG]]37 ; CHECK-NEXT: STRHHui [[PHI]], [[DEF1]], 0 :: (store (s16) into `ptr undef`)38 ; CHECK-NEXT: B %bb.239 bb.0:40 successors: %bb.1(0x80000000)41 42 %0:gpr(s32) = G_IMPLICIT_DEF43 %4:gpr(p0) = G_IMPLICIT_DEF44 %8:fpr(s32) = G_FCONSTANT float 0x7FF800000000000045 46 bb.1:47 successors: %bb.2(0x80000000)48 49 %6:gpr(s32) = G_IMPLICIT_DEF50 %7:gpr(s32) = G_SELECT %0(s32), %6, %651 %1:gpr(s16) = G_TRUNC %7(s32)52 53 bb.2:54 successors: %bb.2(0x80000000)55 56 %3:gpr(s16) = G_PHI %1(s16), %bb.1, %5(s16), %bb.257 %5:fpr(s16) = G_FPTRUNC %8(s32)58 G_STORE %3(s16), %4(p0) :: (store (s16) into `ptr undef`)59 G_BR %bb.260 61...62---63name: test_loop_phi_gpr_to_fpr64alignment: 465legalized: true66regBankSelected: true67selected: false68failedISel: false69tracksRegLiveness: true70liveins: []71machineFunctionInfo: {}72body: |73 ; CHECK-LABEL: name: test_loop_phi_gpr_to_fpr74 ; CHECK: bb.0:75 ; CHECK-NEXT: successors: %bb.1(0x80000000)76 ; CHECK-NEXT: {{ $}}77 ; CHECK-NEXT: [[DEF:%[0-9]+]]:gpr32 = IMPLICIT_DEF78 ; CHECK-NEXT: [[DEF1:%[0-9]+]]:gpr64common = IMPLICIT_DEF79 ; CHECK-NEXT: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 214328934480 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY [[MOVi32imm]]81 ; CHECK-NEXT: {{ $}}82 ; CHECK-NEXT: bb.1:83 ; CHECK-NEXT: successors: %bb.2(0x80000000)84 ; CHECK-NEXT: {{ $}}85 ; CHECK-NEXT: [[DEF2:%[0-9]+]]:gpr32 = IMPLICIT_DEF86 ; CHECK-NEXT: [[ANDSWri:%[0-9]+]]:gpr32 = ANDSWri [[DEF]], 0, implicit-def $nzcv87 ; CHECK-NEXT: [[CSELWr:%[0-9]+]]:gpr32 = CSELWr [[DEF2]], [[DEF2]], 1, implicit $nzcv88 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr32 = COPY [[CSELWr]]89 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr16 = COPY [[COPY1]].hsub90 ; CHECK-NEXT: {{ $}}91 ; CHECK-NEXT: bb.2:92 ; CHECK-NEXT: successors: %bb.2(0x80000000)93 ; CHECK-NEXT: {{ $}}94 ; CHECK-NEXT: [[PHI:%[0-9]+]]:fpr16 = PHI %7, %bb.2, [[COPY2]], %bb.195 ; CHECK-NEXT: [[FCVTHSr:%[0-9]+]]:fpr16 = nofpexcept FCVTHSr [[COPY]], implicit $fpcr96 ; CHECK-NEXT: STRHui [[PHI]], [[DEF1]], 0 :: (store (s16) into `ptr undef`)97 ; CHECK-NEXT: B %bb.298 bb.0:99 successors: %bb.1(0x80000000)100 101 %0:gpr(s32) = G_IMPLICIT_DEF102 %4:gpr(p0) = G_IMPLICIT_DEF103 %8:fpr(s32) = G_FCONSTANT float 0x7FF8000000000000104 105 bb.1:106 successors: %bb.2(0x80000000)107 108 %6:gpr(s32) = G_IMPLICIT_DEF109 %7:gpr(s32) = G_SELECT %0(s32), %6, %6110 %1:gpr(s16) = G_TRUNC %7(s32)111 112 bb.2:113 successors: %bb.2(0x80000000)114 115 %3:fpr(s16) = G_PHI %5(s16), %bb.2, %1(s16), %bb.1116 %5:fpr(s16) = G_FPTRUNC %8(s32)117 G_STORE %3(s16), %4(p0) :: (store (s16) into `ptr undef`)118 G_BR %bb.2119 120...121---122name: multiple_phis123alignment: 4124legalized: true125regBankSelected: true126tracksRegLiveness: true127body: |128 ; CHECK-LABEL: name: multiple_phis129 ; CHECK: bb.0:130 ; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.5(0x40000000)131 ; CHECK-NEXT: liveins: $w0, $w1, $x2132 ; CHECK-NEXT: {{ $}}133 ; CHECK-NEXT: %ptr:gpr64sp = COPY $x2134 ; CHECK-NEXT: %cond_1:gpr32 = IMPLICIT_DEF135 ; CHECK-NEXT: %gpr_1:gpr32 = IMPLICIT_DEF136 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY %gpr_1137 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr16 = COPY [[COPY]].hsub138 ; CHECK-NEXT: TBNZW %cond_1, 0, %bb.5139 ; CHECK-NEXT: B %bb.1140 ; CHECK-NEXT: {{ $}}141 ; CHECK-NEXT: bb.1:142 ; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.3(0x40000000)143 ; CHECK-NEXT: {{ $}}144 ; CHECK-NEXT: %cond_2:gpr32 = IMPLICIT_DEF145 ; CHECK-NEXT: TBNZW %cond_2, 0, %bb.3146 ; CHECK-NEXT: B %bb.2147 ; CHECK-NEXT: {{ $}}148 ; CHECK-NEXT: bb.2:149 ; CHECK-NEXT: successors: %bb.4(0x80000000)150 ; CHECK-NEXT: {{ $}}151 ; CHECK-NEXT: %gpr_2:gpr32 = IMPLICIT_DEF152 ; CHECK-NEXT: B %bb.4153 ; CHECK-NEXT: {{ $}}154 ; CHECK-NEXT: bb.3:155 ; CHECK-NEXT: successors: %bb.4(0x80000000)156 ; CHECK-NEXT: {{ $}}157 ; CHECK-NEXT: %fpr:fpr16 = IMPLICIT_DEF158 ; CHECK-NEXT: {{ $}}159 ; CHECK-NEXT: bb.4:160 ; CHECK-NEXT: successors: %bb.5(0x80000000)161 ; CHECK-NEXT: {{ $}}162 ; CHECK-NEXT: %fp_phi:fpr16 = PHI %fpr, %bb.3, [[COPY1]], %bb.2163 ; CHECK-NEXT: %gp_phi1:gpr32 = PHI %gpr_1, %bb.3, %gpr_2, %bb.2164 ; CHECK-NEXT: %gp_phi2:gpr32 = PHI %gpr_1, %bb.3, %gpr_2, %bb.2165 ; CHECK-NEXT: %gp_phi3:gpr32 = PHI %gpr_1, %bb.3, %gpr_2, %bb.2166 ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:fpr32 = SUBREG_TO_REG 0, %fp_phi, %subreg.hsub167 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr32all = COPY [[SUBREG_TO_REG]]168 ; CHECK-NEXT: {{ $}}169 ; CHECK-NEXT: bb.5:170 ; CHECK-NEXT: %use_fp_phi:gpr32 = PHI %gpr_1, %bb.0, [[COPY2]], %bb.4171 ; CHECK-NEXT: %use_gp_phi1:gpr32 = PHI %gpr_1, %bb.0, %gp_phi1, %bb.4172 ; CHECK-NEXT: %use_gp_phi2:gpr32 = PHI %gpr_1, %bb.0, %gp_phi2, %bb.4173 ; CHECK-NEXT: %use_gp_phi3:gpr32 = PHI %gpr_1, %bb.0, %gp_phi3, %bb.4174 ; CHECK-NEXT: STRHHui %use_fp_phi, %ptr, 0 :: (store (s16))175 ; CHECK-NEXT: STRHHui %use_gp_phi1, %ptr, 0 :: (store (s16))176 ; CHECK-NEXT: STRHHui %use_gp_phi2, %ptr, 0 :: (store (s16))177 ; CHECK-NEXT: STRHHui %use_gp_phi3, %ptr, 0 :: (store (s16))178 ; CHECK-NEXT: RET_ReallyLR179 180 ; The copy we insert in bb.4 should appear after all the phi instructions.181 182 bb.1:183 successors: %bb.2, %bb.6184 liveins: $w0, $w1, $x2185 %ptr:gpr(p0) = COPY $x2186 %cond_1:gpr(s32) = G_IMPLICIT_DEF187 %gpr_1:gpr(s16) = G_IMPLICIT_DEF188 G_BRCOND %cond_1(s32), %bb.6189 G_BR %bb.2190 bb.2:191 successors: %bb.3, %bb.4192 %cond_2:gpr(s32) = G_IMPLICIT_DEF193 G_BRCOND %cond_2(s32), %bb.4194 G_BR %bb.3195 bb.3:196 %gpr_2:gpr(s16) = G_IMPLICIT_DEF197 G_BR %bb.5198 bb.4:199 %fpr:fpr(s16) = G_IMPLICIT_DEF200 bb.5:201 %fp_phi:fpr(s16) = G_PHI %fpr(s16), %bb.4, %gpr_1(s16), %bb.3202 %gp_phi1:gpr(s16) = G_PHI %gpr_1(s16), %bb.4, %gpr_2(s16), %bb.3203 %gp_phi2:gpr(s16) = G_PHI %gpr_1(s16), %bb.4, %gpr_2(s16), %bb.3204 %gp_phi3:gpr(s16) = G_PHI %gpr_1(s16), %bb.4, %gpr_2(s16), %bb.3205 bb.6:206 %use_fp_phi:gpr(s16) = G_PHI %gpr_1(s16), %bb.1, %fp_phi(s16), %bb.5207 %use_gp_phi1:gpr(s16) = G_PHI %gpr_1(s16), %bb.1, %gp_phi1(s16), %bb.5208 %use_gp_phi2:gpr(s16) = G_PHI %gpr_1(s16), %bb.1, %gp_phi2(s16), %bb.5209 %use_gp_phi3:gpr(s16) = G_PHI %gpr_1(s16), %bb.1, %gp_phi3(s16), %bb.5210 G_STORE %use_fp_phi(s16), %ptr(p0) :: (store (s16))211 G_STORE %use_gp_phi1(s16), %ptr(p0) :: (store (s16))212 G_STORE %use_gp_phi2(s16), %ptr(p0) :: (store (s16))213 G_STORE %use_gp_phi3(s16), %ptr(p0) :: (store (s16))214 RET_ReallyLR215...216