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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=aarch64-unknown-unknown -verify-machineinstrs -O0 -run-pass=regbankselect -global-isel-abort=1 %s -o - | FileCheck %s3 4name: v2s32_fpr5alignment: 46legalized: true7tracksRegLiveness: true8registers:9 - { id: 0, class: _ }10 - { id: 1, class: _ }11 - { id: 2, class: _ }12body: |13 bb.1.entry:14 liveins: $d015 16 %0:_(<2 x s32>) = COPY $d017 %2:_(s64) = G_CONSTANT i64 118 %1:_(s32) = G_EXTRACT_VECTOR_ELT %0(<2 x s32>), %2(s64)19 $s0 = COPY %1(s32)20 RET_ReallyLR implicit $s021 22...23---24name: v4s32_gpr25alignment: 426legalized: true27tracksRegLiveness: true28registers:29 - { id: 0, class: _ }30 - { id: 1, class: _ }31 - { id: 2, class: _ }32body: |33 bb.1.entry:34 liveins: $q035 36 ; CHECK-LABEL: name: v4s32_gpr37 ; CHECK: liveins: $q038 ; CHECK-NEXT: {{ $}}39 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr(<4 x s32>) = COPY $q040 ; CHECK-NEXT: [[C:%[0-9]+]]:gpr(s64) = G_CONSTANT i64 041 ; CHECK-NEXT: [[EVEC:%[0-9]+]]:fpr(s32) = G_EXTRACT_VECTOR_ELT [[COPY]](<4 x s32>), [[C]](s64)42 ; CHECK-NEXT: $s0 = COPY [[EVEC]](s32)43 ; CHECK-NEXT: RET_ReallyLR implicit $s044 %0:_(<4 x s32>) = COPY $q045 %2:_(s64) = G_CONSTANT i64 046 %1:_(s32) = G_EXTRACT_VECTOR_ELT %0(<4 x s32>), %2(s64)47 $s0 = COPY %1(s32)48 RET_ReallyLR implicit $s049 50...51---52name: v2s64_fpr53alignment: 454legalized: true55tracksRegLiveness: true56registers:57 - { id: 0, class: _ }58 - { id: 1, class: _ }59 - { id: 2, class: _ }60body: |61 bb.1.entry:62 liveins: $q063 64 ; CHECK-LABEL: name: v2s64_fpr65 ; CHECK: liveins: $q066 ; CHECK-NEXT: {{ $}}67 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr(<2 x s64>) = COPY $q068 ; CHECK-NEXT: [[C:%[0-9]+]]:gpr(s64) = G_CONSTANT i64 269 ; CHECK-NEXT: [[EVEC:%[0-9]+]]:fpr(s64) = G_EXTRACT_VECTOR_ELT [[COPY]](<2 x s64>), [[C]](s64)70 ; CHECK-NEXT: $d0 = COPY [[EVEC]](s64)71 ; CHECK-NEXT: RET_ReallyLR implicit $d072 %0:_(<2 x s64>) = COPY $q073 %2:_(s64) = G_CONSTANT i64 274 %1:_(s64) = G_EXTRACT_VECTOR_ELT %0(<2 x s64>), %2(s64)75 $d0 = COPY %1(s64)76 RET_ReallyLR implicit $d077 78...79---80name: v4s16_fpr81alignment: 482legalized: true83tracksRegLiveness: true84registers:85 - { id: 0, class: _ }86 - { id: 1, class: _ }87 - { id: 2, class: _ }88body: |89 bb.1.entry:90 liveins: $d091 92 ; CHECK-LABEL: name: v4s16_fpr93 ; CHECK: liveins: $d094 ; CHECK-NEXT: {{ $}}95 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr(<4 x s16>) = COPY $d096 ; CHECK-NEXT: [[C:%[0-9]+]]:gpr(s64) = G_CONSTANT i64 197 ; CHECK-NEXT: [[EVEC:%[0-9]+]]:fpr(s16) = G_EXTRACT_VECTOR_ELT [[COPY]](<4 x s16>), [[C]](s64)98 ; CHECK-NEXT: $h0 = COPY [[EVEC]](s16)99 ; CHECK-NEXT: RET_ReallyLR implicit $h0100 %0:_(<4 x s16>) = COPY $d0101 %2:_(s64) = G_CONSTANT i64 1102 %1:_(s16) = G_EXTRACT_VECTOR_ELT %0(<4 x s16>), %2(s64)103 $h0 = COPY %1(s16)104 RET_ReallyLR implicit $h0105 106...107