28 lines · plain
1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=aarch64 -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s3 4...5---6name: vector7legalized: true8tracksRegLiveness: true9body: |10 bb.0:11 liveins: $q0, $q112 ; Vectors should always end up on a FPR.13 14 ; CHECK-LABEL: name: vector15 ; CHECK: liveins: $q0, $q116 ; CHECK-NEXT: {{ $}}17 ; CHECK-NEXT: %x:fpr(<2 x s64>) = COPY $q018 ; CHECK-NEXT: %y:fpr(<2 x s64>) = COPY $q119 ; CHECK-NEXT: %fcmp:fpr(<2 x s64>) = G_FCMP floatpred(olt), %x(<2 x s64>), %y20 ; CHECK-NEXT: $q0 = COPY %fcmp(<2 x s64>)21 ; CHECK-NEXT: RET_ReallyLR implicit $q022 %x:_(<2 x s64>) = COPY $q023 %y:_(<2 x s64>) = COPY $q124 %fcmp:_(<2 x s64>) = G_FCMP floatpred(olt), %x:_(<2 x s64>), %y:_25 $q0 = COPY %fcmp26 RET_ReallyLR implicit $q027...28