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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -verify-machineinstrs -mtriple aarch64-unknown-unknown -run-pass=regbankselect %s -o - | FileCheck %s3 4# The following should hold here:5#6# 1) The first and second operands of G_INSERT_VECTOR_ELT should be FPRs since7# they are vectors.8#9# 2) The third operand should be on the register bank given in the test name10# (e.g, v4s32_fpr). AArch64 supports native inserts of GPRs, so we need to11# preserve that.12#13# 3) The fourth operand should be a GPR, since it's a constant.14 15name: v4s32_fpr16alignment: 417legalized: true18tracksRegLiveness: true19body: |20 bb.0:21 liveins: $q1, $s022 23 ; CHECK-LABEL: name: v4s32_fpr24 ; CHECK: liveins: $q1, $s025 ; CHECK: [[COPY:%[0-9]+]]:fpr(s32) = COPY $s026 ; CHECK: [[COPY1:%[0-9]+]]:fpr(<4 x s32>) = COPY $q127 ; CHECK: [[C:%[0-9]+]]:gpr(s64) = G_CONSTANT i64 128 ; CHECK: [[IVEC:%[0-9]+]]:fpr(<4 x s32>) = G_INSERT_VECTOR_ELT [[COPY1]], [[COPY]](s32), [[C]](s64)29 ; CHECK: $q0 = COPY [[IVEC]](<4 x s32>)30 ; CHECK: RET_ReallyLR implicit $q031 %0:_(s32) = COPY $s032 %1:_(<4 x s32>) = COPY $q133 %3:_(s64) = G_CONSTANT i64 134 %2:_(<4 x s32>) = G_INSERT_VECTOR_ELT %1, %0(s32), %3(s64)35 $q0 = COPY %2(<4 x s32>)36 RET_ReallyLR implicit $q037 38...39---40name: v4s32_gpr41alignment: 442legalized: true43tracksRegLiveness: true44body: |45 bb.0:46 liveins: $q0, $w047 48 ; CHECK-LABEL: name: v4s32_gpr49 ; CHECK: liveins: $q0, $w050 ; CHECK-NEXT: {{ $}}51 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr(s32) = COPY $w052 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr(<4 x s32>) = COPY $q053 ; CHECK-NEXT: [[C:%[0-9]+]]:gpr(s64) = G_CONSTANT i64 154 ; CHECK-NEXT: [[IVEC:%[0-9]+]]:fpr(<4 x s32>) = G_INSERT_VECTOR_ELT [[COPY1]], [[COPY]](s32), [[C]](s64)55 ; CHECK-NEXT: $q0 = COPY [[IVEC]](<4 x s32>)56 ; CHECK-NEXT: RET_ReallyLR implicit $q057 %0:_(s32) = COPY $w058 %1:_(<4 x s32>) = COPY $q059 %3:_(s64) = G_CONSTANT i64 160 %2:_(<4 x s32>) = G_INSERT_VECTOR_ELT %1, %0(s32), %3(s64)61 $q0 = COPY %2(<4 x s32>)62 RET_ReallyLR implicit $q063 64...65---66name: v2s64_fpr67alignment: 468legalized: true69tracksRegLiveness: true70body: |71 bb.0:72 liveins: $d0, $q173 74 ; CHECK-LABEL: name: v2s64_fpr75 ; CHECK: liveins: $d0, $q176 ; CHECK-NEXT: {{ $}}77 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr(s64) = COPY $d078 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr(<2 x s64>) = COPY $q179 ; CHECK-NEXT: [[C:%[0-9]+]]:gpr(s64) = G_CONSTANT i64 180 ; CHECK-NEXT: [[IVEC:%[0-9]+]]:fpr(<2 x s64>) = G_INSERT_VECTOR_ELT [[COPY1]], [[COPY]](s64), [[C]](s64)81 ; CHECK-NEXT: $q0 = COPY [[IVEC]](<2 x s64>)82 ; CHECK-NEXT: RET_ReallyLR implicit $q083 %0:_(s64) = COPY $d084 %1:_(<2 x s64>) = COPY $q185 %3:_(s64) = G_CONSTANT i64 186 %2:_(<2 x s64>) = G_INSERT_VECTOR_ELT %1, %0(s64), %3(s64)87 $q0 = COPY %2(<2 x s64>)88 RET_ReallyLR implicit $q089 90...91---92name: v2s64_gpr93alignment: 494legalized: true95tracksRegLiveness: true96body: |97 bb.0:98 liveins: $q0, $x099 100 ; CHECK-LABEL: name: v2s64_gpr101 ; CHECK: liveins: $q0, $x0102 ; CHECK-NEXT: {{ $}}103 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr(s64) = COPY $x0104 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr(<2 x s64>) = COPY $q0105 ; CHECK-NEXT: [[C:%[0-9]+]]:gpr(s64) = G_CONSTANT i64 0106 ; CHECK-NEXT: [[IVEC:%[0-9]+]]:fpr(<2 x s64>) = G_INSERT_VECTOR_ELT [[COPY1]], [[COPY]](s64), [[C]](s64)107 ; CHECK-NEXT: $q0 = COPY [[IVEC]](<2 x s64>)108 ; CHECK-NEXT: RET_ReallyLR implicit $q0109 %0:_(s64) = COPY $x0110 %1:_(<2 x s64>) = COPY $q0111 %3:_(s64) = G_CONSTANT i64 0112 %2:_(<2 x s64>) = G_INSERT_VECTOR_ELT %1, %0(s64), %3(s64)113 $q0 = COPY %2(<2 x s64>)114 RET_ReallyLR implicit $q0115 116...117---118name: v2s32_fpr119alignment: 4120legalized: true121tracksRegLiveness: true122body: |123 bb.0:124 liveins: $d1, $s0125 126 ; CHECK-LABEL: name: v2s32_fpr127 ; CHECK: liveins: $d1, $s0128 ; CHECK-NEXT: {{ $}}129 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr(s32) = COPY $s0130 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr(<2 x s32>) = COPY $d1131 ; CHECK-NEXT: [[C:%[0-9]+]]:gpr(s64) = G_CONSTANT i64 1132 ; CHECK-NEXT: [[IVEC:%[0-9]+]]:fpr(<2 x s32>) = G_INSERT_VECTOR_ELT [[COPY1]], [[COPY]](s32), [[C]](s64)133 ; CHECK-NEXT: $d0 = COPY [[IVEC]](<2 x s32>)134 ; CHECK-NEXT: RET_ReallyLR implicit $d0135 %0:_(s32) = COPY $s0136 %1:_(<2 x s32>) = COPY $d1137 %3:_(s64) = G_CONSTANT i64 1138 %2:_(<2 x s32>) = G_INSERT_VECTOR_ELT %1, %0(s32), %3(s64)139 $d0 = COPY %2(<2 x s32>)140 RET_ReallyLR implicit $d0141 142...143---144name: v2s32_gpr145alignment: 4146legalized: true147tracksRegLiveness: true148body: |149 bb.0:150 liveins: $d0, $w0151 152 ; CHECK-LABEL: name: v2s32_gpr153 ; CHECK: liveins: $d0, $w0154 ; CHECK-NEXT: {{ $}}155 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr(s32) = COPY $w0156 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr(<2 x s32>) = COPY $d0157 ; CHECK-NEXT: [[C:%[0-9]+]]:gpr(s64) = G_CONSTANT i64 1158 ; CHECK-NEXT: [[IVEC:%[0-9]+]]:fpr(<2 x s32>) = G_INSERT_VECTOR_ELT [[COPY1]], [[COPY]](s32), [[C]](s64)159 ; CHECK-NEXT: $d0 = COPY [[IVEC]](<2 x s32>)160 ; CHECK-NEXT: RET_ReallyLR implicit $d0161 %0:_(s32) = COPY $w0162 %1:_(<2 x s32>) = COPY $d0163 %3:_(s64) = G_CONSTANT i64 1164 %2:_(<2 x s32>) = G_INSERT_VECTOR_ELT %1, %0(s32), %3(s64)165 $d0 = COPY %2(<2 x s32>)166 RET_ReallyLR implicit $d0167 168...169