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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -O0 -mtriple arm64-- -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s3---4name: build_vec_f165alignment: 46legalized: true7tracksRegLiveness: true8body: |9 bb.0:10 liveins: $w011 12 ; Check that s16 operands are assigned fpr as we don't have 16 bit gpr regs.13 ; CHECK-LABEL: name: build_vec_f1614 ; CHECK: liveins: $w015 ; CHECK-NEXT: {{ $}}16 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr(s32) = COPY $w017 ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:gpr(s16) = G_TRUNC [[COPY]](s32)18 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr(s16) = COPY [[TRUNC]](s16)19 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr(s16) = COPY [[TRUNC]](s16)20 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:fpr(s16) = COPY [[TRUNC]](s16)21 ; CHECK-NEXT: [[COPY4:%[0-9]+]]:fpr(s16) = COPY [[TRUNC]](s16)22 ; CHECK-NEXT: [[COPY5:%[0-9]+]]:fpr(s16) = COPY [[TRUNC]](s16)23 ; CHECK-NEXT: [[COPY6:%[0-9]+]]:fpr(s16) = COPY [[TRUNC]](s16)24 ; CHECK-NEXT: [[COPY7:%[0-9]+]]:fpr(s16) = COPY [[TRUNC]](s16)25 ; CHECK-NEXT: [[COPY8:%[0-9]+]]:fpr(s16) = COPY [[TRUNC]](s16)26 ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:fpr(<8 x s16>) = G_BUILD_VECTOR [[COPY1]](s16), [[COPY2]](s16), [[COPY3]](s16), [[COPY4]](s16), [[COPY5]](s16), [[COPY6]](s16), [[COPY7]](s16), [[COPY8]](s16)27 ; CHECK-NEXT: $q0 = COPY [[BUILD_VECTOR]](<8 x s16>)28 ; CHECK-NEXT: RET_ReallyLR implicit $q029 %0:_(s32) = COPY $w030 %1:_(s16) = G_TRUNC %0(s32)31 %2:_(<8 x s16>) = G_BUILD_VECTOR %1(s16), %1(s16), %1(s16), %1(s16), %1(s16), %1(s16), %1(s16), %1(s16)32 $q0 = COPY %2(<8 x s16>)33 RET_ReallyLR implicit $q034 35...36---37name: g_constant_operands_on_gpr38alignment: 439legalized: true40tracksRegLiveness: true41body: |42 bb.1:43 ; Check that we assign GPR to the operands even though they're < 32b in size.44 ; They're all constant, so we can select it via a constant-pool load if needed45 ; and this form is more amenable to selection by patterns (without x-bank copies).46 ; CHECK-LABEL: name: g_constant_operands_on_gpr47 ; CHECK: [[C:%[0-9]+]]:gpr(s8) = G_CONSTANT i8 448 ; CHECK-NEXT: [[C1:%[0-9]+]]:gpr(s8) = G_CONSTANT i8 1049 ; CHECK-NEXT: [[C2:%[0-9]+]]:gpr(s8) = G_CONSTANT i8 350 ; CHECK-NEXT: [[C3:%[0-9]+]]:gpr(s8) = G_CONSTANT i8 1151 ; CHECK-NEXT: [[C4:%[0-9]+]]:gpr(s8) = G_CONSTANT i8 1552 ; CHECK-NEXT: [[C5:%[0-9]+]]:gpr(s8) = G_CONSTANT i8 4453 ; CHECK-NEXT: [[C6:%[0-9]+]]:gpr(s8) = G_CONSTANT i8 2254 ; CHECK-NEXT: [[C7:%[0-9]+]]:gpr(s8) = G_CONSTANT i8 1955 ; CHECK-NEXT: [[C8:%[0-9]+]]:gpr(s8) = G_CONSTANT i8 5556 ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:fpr(<16 x s8>) = G_BUILD_VECTOR [[C]](s8), [[C1]](s8), [[C2]](s8), [[C3]](s8), [[C4]](s8), [[C]](s8), [[C1]](s8), [[C5]](s8), [[C6]](s8), [[C4]](s8), [[C]](s8), [[C7]](s8), [[C2]](s8), [[C3]](s8), [[C4]](s8), [[C8]](s8)57 ; CHECK-NEXT: $q0 = COPY [[BUILD_VECTOR]](<16 x s8>)58 ; CHECK-NEXT: RET_ReallyLR implicit $q059 %1:_(s8) = G_CONSTANT i8 460 %2:_(s8) = G_CONSTANT i8 1061 %3:_(s8) = G_CONSTANT i8 362 %4:_(s8) = G_CONSTANT i8 1163 %5:_(s8) = G_CONSTANT i8 1564 %6:_(s8) = G_CONSTANT i8 4465 %7:_(s8) = G_CONSTANT i8 2266 %8:_(s8) = G_CONSTANT i8 1967 %9:_(s8) = G_CONSTANT i8 5568 %0:_(<16 x s8>) = G_BUILD_VECTOR %1(s8), %2(s8), %3(s8), %4(s8), %5(s8), %1(s8), %2(s8), %6(s8), %7(s8), %5(s8), %1(s8), %8(s8), %3(s8), %4(s8), %5(s8), %9(s8)69 $q0 = COPY %0(<16 x s8>)70 RET_ReallyLR implicit $q071 72...73---74name: fed_by_fp_load75alignment: 476legalized: true77tracksRegLiveness: true78liveins:79 - { reg: '$x0' }80 - { reg: '$x1' }81 - { reg: '$x2' }82 - { reg: '$s0' }83frameInfo:84 maxAlignment: 185body: |86 bb.1:87 liveins: $s0, $x0, $x1, $x288 89 ; CHECK-LABEL: name: fed_by_fp_load90 ; CHECK: liveins: $s0, $x0, $x1, $x291 ; CHECK-NEXT: {{ $}}92 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr(p0) = COPY $x093 ; CHECK-NEXT: [[C:%[0-9]+]]:gpr(s64) = G_CONSTANT i64 32894 ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:gpr(p0) = G_PTR_ADD [[COPY]], [[C]](s64)95 ; CHECK-NEXT: [[C1:%[0-9]+]]:gpr(s64) = G_CONSTANT i64 34496 ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:gpr(p0) = G_PTR_ADD [[COPY]], [[C1]](s64)97 ; CHECK-NEXT: [[LOAD:%[0-9]+]]:fpr(s32) = G_LOAD [[PTR_ADD]](p0) :: (load (s32))98 ; CHECK-NEXT: [[LOAD1:%[0-9]+]]:fpr(s32) = G_LOAD [[PTR_ADD1]](p0) :: (load (s32))99 ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:fpr(<2 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LOAD1]](s32)100 ; CHECK-NEXT: $d0 = COPY [[BUILD_VECTOR]](<2 x s32>)101 ; CHECK-NEXT: RET_ReallyLR implicit $d0102 %0:_(p0) = COPY $x0103 %4:_(s64) = G_CONSTANT i64 328104 %5:_(p0) = G_PTR_ADD %0, %4(s64)105 %6:_(s64) = G_CONSTANT i64 344106 %7:_(p0) = G_PTR_ADD %0, %6(s64)107 %15:_(s32) = G_LOAD %5(p0) :: (load (s32))108 %20:_(s32) = G_LOAD %7(p0) :: (load (s32))109 %21:_(<2 x s32>) = G_BUILD_VECTOR %15(s32), %20(s32)110 $d0 = COPY %21(<2 x s32>)111 RET_ReallyLR implicit $d0112 113...114