137 lines · plain
1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=aarch64-apple-ios -run-pass=instruction-select %s -o - | FileCheck %s3 4...5---6name: v4s167legalized: true8regBankSelected: true9tracksRegLiveness: true10body: |11 bb.0:12 liveins: $d013 14 ; CHECK-LABEL: name: v4s1615 ; CHECK: liveins: $d016 ; CHECK-NEXT: {{ $}}17 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d018 ; CHECK-NEXT: [[ABSv4i16_:%[0-9]+]]:fpr64 = ABSv4i16 [[COPY]]19 ; CHECK-NEXT: $d0 = COPY [[ABSv4i16_]]20 ; CHECK-NEXT: RET_ReallyLR implicit $d021 %0:fpr(<4 x s16>) = COPY $d022 %1:fpr(<4 x s16>) = G_ABS %023 $d0 = COPY %1(<4 x s16>)24 RET_ReallyLR implicit $d025 26...27---28name: v8s1629legalized: true30regBankSelected: true31tracksRegLiveness: true32body: |33 bb.0:34 liveins: $q035 36 ; CHECK-LABEL: name: v8s1637 ; CHECK: liveins: $q038 ; CHECK-NEXT: {{ $}}39 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q040 ; CHECK-NEXT: [[ABSv8i16_:%[0-9]+]]:fpr128 = ABSv8i16 [[COPY]]41 ; CHECK-NEXT: $q0 = COPY [[ABSv8i16_]]42 ; CHECK-NEXT: RET_ReallyLR implicit $q043 %0:fpr(<8 x s16>) = COPY $q044 %1:fpr(<8 x s16>) = G_ABS %045 $q0 = COPY %1(<8 x s16>)46 RET_ReallyLR implicit $q047 48...49---50name: v2s3251legalized: true52regBankSelected: true53tracksRegLiveness: true54body: |55 bb.0:56 liveins: $d057 58 ; CHECK-LABEL: name: v2s3259 ; CHECK: liveins: $d060 ; CHECK-NEXT: {{ $}}61 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d062 ; CHECK-NEXT: [[ABSv2i32_:%[0-9]+]]:fpr64 = ABSv2i32 [[COPY]]63 ; CHECK-NEXT: $d0 = COPY [[ABSv2i32_]]64 ; CHECK-NEXT: RET_ReallyLR implicit $d065 %0:fpr(<2 x s32>) = COPY $d066 %1:fpr(<2 x s32>) = G_ABS %067 $d0 = COPY %1(<2 x s32>)68 RET_ReallyLR implicit $d069 70...71---72name: v4s3273legalized: true74regBankSelected: true75tracksRegLiveness: true76body: |77 bb.0:78 liveins: $q079 80 ; CHECK-LABEL: name: v4s3281 ; CHECK: liveins: $q082 ; CHECK-NEXT: {{ $}}83 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q084 ; CHECK-NEXT: [[ABSv4i32_:%[0-9]+]]:fpr128 = ABSv4i32 [[COPY]]85 ; CHECK-NEXT: $q0 = COPY [[ABSv4i32_]]86 ; CHECK-NEXT: RET_ReallyLR implicit $q087 %0:fpr(<4 x s32>) = COPY $q088 %1:fpr(<4 x s32>) = G_ABS %089 $q0 = COPY %1(<4 x s32>)90 RET_ReallyLR implicit $q091 92...93---94name: v4s895legalized: true96regBankSelected: true97tracksRegLiveness: true98body: |99 bb.0:100 liveins: $d0101 102 ; CHECK-LABEL: name: v4s8103 ; CHECK: liveins: $d0104 ; CHECK-NEXT: {{ $}}105 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0106 ; CHECK-NEXT: [[ABSv8i8_:%[0-9]+]]:fpr64 = ABSv8i8 [[COPY]]107 ; CHECK-NEXT: $d0 = COPY [[ABSv8i8_]]108 ; CHECK-NEXT: RET_ReallyLR implicit $d0109 %0:fpr(<8 x s8>) = COPY $d0110 %1:fpr(<8 x s8>) = G_ABS %0111 $d0 = COPY %1(<8 x s8>)112 RET_ReallyLR implicit $d0113 114...115---116name: v16s8117legalized: true118regBankSelected: true119tracksRegLiveness: true120body: |121 bb.0:122 liveins: $q0123 124 ; CHECK-LABEL: name: v16s8125 ; CHECK: liveins: $q0126 ; CHECK-NEXT: {{ $}}127 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0128 ; CHECK-NEXT: [[ABSv16i8_:%[0-9]+]]:fpr128 = ABSv16i8 [[COPY]]129 ; CHECK-NEXT: $q0 = COPY [[ABSv16i8_]]130 ; CHECK-NEXT: RET_ReallyLR implicit $q0131 %0:fpr(<16 x s8>) = COPY $q0132 %1:fpr(<16 x s8>) = G_ABS %0133 $q0 = COPY %1(<16 x s8>)134 RET_ReallyLR implicit $q0135 136...137