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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=aarch64-unknown-unknown -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s3 4---5name: add_sext_s32_to_s646alignment: 47legalized: true8regBankSelected: true9tracksRegLiveness: true10machineFunctionInfo: {}11body: |12 bb.0:13 liveins: $w1, $x214 ; CHECK-LABEL: name: add_sext_s32_to_s6415 ; CHECK: liveins: $w1, $x216 ; CHECK-NEXT: {{ $}}17 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w118 ; CHECK-NEXT: %add_lhs:gpr64sp = COPY $x219 ; CHECK-NEXT: %res:gpr64sp = ADDXrx %add_lhs, [[COPY]], 4820 ; CHECK-NEXT: $x3 = COPY %res21 ; CHECK-NEXT: RET_ReallyLR implicit $x322 %1:gpr(s32) = COPY $w123 %ext:gpr(s64) = G_SEXT %1(s32)24 %add_lhs:gpr(s64) = COPY $x225 %res:gpr(s64) = G_ADD %add_lhs, %ext26 $x3 = COPY %res(s64)27 RET_ReallyLR implicit $x328...29---30name: add_and_s32_to_s6431alignment: 432legalized: true33regBankSelected: true34tracksRegLiveness: true35machineFunctionInfo: {}36body: |37 bb.0:38 liveins: $x1, $x239 ; CHECK-LABEL: name: add_and_s32_to_s6440 ; CHECK: liveins: $x1, $x241 ; CHECK-NEXT: {{ $}}42 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64all = COPY $x143 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32all = COPY [[COPY]].sub_3244 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr32 = COPY [[COPY1]]45 ; CHECK-NEXT: %add_lhs:gpr64sp = COPY $x246 ; CHECK-NEXT: %res:gpr64sp = ADDXrx %add_lhs, [[COPY2]], 1647 ; CHECK-NEXT: $x3 = COPY %res48 ; CHECK-NEXT: RET_ReallyLR implicit $x349 %1:gpr(s64) = COPY $x150 %mask:gpr(s64) = G_CONSTANT i64 4294967295 ; 0xffff51 %ext:gpr(s64) = G_AND %1(s64), %mask52 %add_lhs:gpr(s64) = COPY $x253 %res:gpr(s64) = G_ADD %add_lhs, %ext54 $x3 = COPY %res(s64)55 RET_ReallyLR implicit $x356...57---58name: add_sext_s16_to_s3259alignment: 460legalized: true61regBankSelected: true62tracksRegLiveness: true63machineFunctionInfo: {}64body: |65 bb.0:66 liveins: $w1, $w2, $x267 ; CHECK-LABEL: name: add_sext_s16_to_s3268 ; CHECK: liveins: $w1, $w2, $x269 ; CHECK-NEXT: {{ $}}70 ; CHECK-NEXT: %wide_1:gpr32 = COPY $w171 ; CHECK-NEXT: %add_lhs:gpr32sp = COPY $w272 ; CHECK-NEXT: %res:gpr32sp = ADDWrx %add_lhs, %wide_1, 4073 ; CHECK-NEXT: $w3 = COPY %res74 ; CHECK-NEXT: RET_ReallyLR implicit $w375 %wide_1:gpr(s32) = COPY $w176 %1:gpr(s16) = G_TRUNC %wide_177 %ext:gpr(s32) = G_SEXT %1(s16)78 %add_lhs:gpr(s32) = COPY $w279 %res:gpr(s32) = G_ADD %add_lhs, %ext80 $w3 = COPY %res(s32)81 RET_ReallyLR implicit $w382...83---84name: add_zext_s16_to_s3285alignment: 486legalized: true87regBankSelected: true88tracksRegLiveness: true89machineFunctionInfo: {}90body: |91 bb.0:92 liveins: $w1, $w2, $x293 ; CHECK-LABEL: name: add_zext_s16_to_s3294 ; CHECK: liveins: $w1, $w2, $x295 ; CHECK-NEXT: {{ $}}96 ; CHECK-NEXT: %wide_1:gpr32 = COPY $w197 ; CHECK-NEXT: %add_lhs:gpr32sp = COPY $w298 ; CHECK-NEXT: %res:gpr32sp = ADDWrx %add_lhs, %wide_1, 899 ; CHECK-NEXT: $w3 = COPY %res100 ; CHECK-NEXT: RET_ReallyLR implicit $w3101 %wide_1:gpr(s32) = COPY $w1102 %1:gpr(s16) = G_TRUNC %wide_1103 %ext:gpr(s32) = G_ZEXT %1(s16)104 %add_lhs:gpr(s32) = COPY $w2105 %res:gpr(s32) = G_ADD %add_lhs, %ext106 $w3 = COPY %res(s32)107 RET_ReallyLR implicit $w3108...109---110name: add_anyext_s16_to_s32111alignment: 4112legalized: true113regBankSelected: true114tracksRegLiveness: true115machineFunctionInfo: {}116body: |117 bb.0:118 liveins: $w1, $w2, $x2119 ; CHECK-LABEL: name: add_anyext_s16_to_s32120 ; CHECK: liveins: $w1, $w2, $x2121 ; CHECK-NEXT: {{ $}}122 ; CHECK-NEXT: %wide_1:gpr32 = COPY $w1123 ; CHECK-NEXT: %add_lhs:gpr32sp = COPY $w2124 ; CHECK-NEXT: %res:gpr32sp = ADDWrx %add_lhs, %wide_1, 8125 ; CHECK-NEXT: $w3 = COPY %res126 ; CHECK-NEXT: RET_ReallyLR implicit $w3127 %wide_1:gpr(s32) = COPY $w1128 %1:gpr(s16) = G_TRUNC %wide_1129 %ext:gpr(s32) = G_ANYEXT %1(s16)130 %add_lhs:gpr(s32) = COPY $w2131 %res:gpr(s32) = G_ADD %add_lhs, %ext132 $w3 = COPY %res(s32)133 RET_ReallyLR implicit $w3134...135---136name: add_and_s16_to_s32_uxtb137alignment: 4138legalized: true139regBankSelected: true140tracksRegLiveness: true141machineFunctionInfo: {}142body: |143 bb.0:144 liveins: $w1, $w2, $x2145 ; CHECK-LABEL: name: add_and_s16_to_s32_uxtb146 ; CHECK: liveins: $w1, $w2, $x2147 ; CHECK-NEXT: {{ $}}148 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w1149 ; CHECK-NEXT: %add_lhs:gpr32sp = COPY $w2150 ; CHECK-NEXT: %res:gpr32sp = ADDWrx %add_lhs, [[COPY]], 0151 ; CHECK-NEXT: $w3 = COPY %res152 ; CHECK-NEXT: RET_ReallyLR implicit $w3153 %1:gpr(s32) = COPY $w1154 %mask:gpr(s32) = G_CONSTANT i32 255 ; 0xff155 %ext:gpr(s32) = G_AND %1(s32), %mask156 %add_lhs:gpr(s32) = COPY $w2157 %res:gpr(s32) = G_ADD %add_lhs, %ext158 $w3 = COPY %res(s32)159 RET_ReallyLR implicit $w3160...161---162name: add_and_s16_to_s32_uxth163alignment: 4164legalized: true165regBankSelected: true166tracksRegLiveness: true167machineFunctionInfo: {}168body: |169 bb.0:170 liveins: $w1, $w2, $x2171 ; CHECK-LABEL: name: add_and_s16_to_s32_uxth172 ; CHECK: liveins: $w1, $w2, $x2173 ; CHECK-NEXT: {{ $}}174 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w1175 ; CHECK-NEXT: %add_lhs:gpr32sp = COPY $w2176 ; CHECK-NEXT: %res:gpr32sp = ADDWrx %add_lhs, [[COPY]], 8177 ; CHECK-NEXT: $w3 = COPY %res178 ; CHECK-NEXT: RET_ReallyLR implicit $w3179 %1:gpr(s32) = COPY $w1180 %mask:gpr(s32) = G_CONSTANT i32 65535 ; 0xffff181 %ext:gpr(s32) = G_AND %1(s32), %mask182 %add_lhs:gpr(s32) = COPY $w2183 %res:gpr(s32) = G_ADD %add_lhs, %ext184 $w3 = COPY %res(s32)185 RET_ReallyLR implicit $w3186...187---188name: add_sext_s8_to_s32189alignment: 4190legalized: true191regBankSelected: true192tracksRegLiveness: true193machineFunctionInfo: {}194body: |195 bb.0:196 liveins: $w1, $w2, $x2197 ; CHECK-LABEL: name: add_sext_s8_to_s32198 ; CHECK: liveins: $w1, $w2, $x2199 ; CHECK-NEXT: {{ $}}200 ; CHECK-NEXT: %wide_1:gpr32 = COPY $w1201 ; CHECK-NEXT: %add_lhs:gpr32sp = COPY $w2202 ; CHECK-NEXT: %res:gpr32sp = ADDWrx %add_lhs, %wide_1, 32203 ; CHECK-NEXT: $w3 = COPY %res204 ; CHECK-NEXT: RET_ReallyLR implicit $w3205 %wide_1:gpr(s32) = COPY $w1206 %1:gpr(s8) = G_TRUNC %wide_1207 %ext:gpr(s32) = G_SEXT %1(s8)208 %add_lhs:gpr(s32) = COPY $w2209 %res:gpr(s32) = G_ADD %add_lhs, %ext210 $w3 = COPY %res(s32)211 RET_ReallyLR implicit $w3212...213---214name: add_zext_s8_to_s32215alignment: 4216legalized: true217regBankSelected: true218tracksRegLiveness: true219machineFunctionInfo: {}220body: |221 bb.0:222 liveins: $w1, $w2, $x2223 ; CHECK-LABEL: name: add_zext_s8_to_s32224 ; CHECK: liveins: $w1, $w2, $x2225 ; CHECK-NEXT: {{ $}}226 ; CHECK-NEXT: %wide_1:gpr32 = COPY $w1227 ; CHECK-NEXT: %add_lhs:gpr32sp = COPY $w2228 ; CHECK-NEXT: %res:gpr32sp = ADDWrx %add_lhs, %wide_1, 0229 ; CHECK-NEXT: $w3 = COPY %res230 ; CHECK-NEXT: RET_ReallyLR implicit $w3231 %wide_1:gpr(s32) = COPY $w1232 %1:gpr(s8) = G_TRUNC %wide_1233 %ext:gpr(s32) = G_ZEXT %1(s8)234 %add_lhs:gpr(s32) = COPY $w2235 %res:gpr(s32) = G_ADD %add_lhs, %ext236 $w3 = COPY %res(s32)237 RET_ReallyLR implicit $w3238...239---240name: add_anyext_s8_to_s32241alignment: 4242legalized: true243regBankSelected: true244tracksRegLiveness: true245machineFunctionInfo: {}246body: |247 bb.0:248 liveins: $w1, $w2, $x2249 ; CHECK-LABEL: name: add_anyext_s8_to_s32250 ; CHECK: liveins: $w1, $w2, $x2251 ; CHECK-NEXT: {{ $}}252 ; CHECK-NEXT: %wide_1:gpr32 = COPY $w1253 ; CHECK-NEXT: %add_lhs:gpr32sp = COPY $w2254 ; CHECK-NEXT: %res:gpr32sp = ADDWrx %add_lhs, %wide_1, 0255 ; CHECK-NEXT: $w3 = COPY %res256 ; CHECK-NEXT: RET_ReallyLR implicit $w3257 %wide_1:gpr(s32) = COPY $w1258 %1:gpr(s8) = G_TRUNC %wide_1259 %ext:gpr(s32) = G_ANYEXT %1(s8)260 %add_lhs:gpr(s32) = COPY $w2261 %res:gpr(s32) = G_ADD %add_lhs, %ext262 $w3 = COPY %res(s32)263 RET_ReallyLR implicit $w3264...265---266name: add_sext_with_shl267alignment: 4268legalized: true269regBankSelected: true270tracksRegLiveness: true271machineFunctionInfo: {}272body: |273 bb.0:274 liveins: $w1, $w2, $x2275 ; CHECK-LABEL: name: add_sext_with_shl276 ; CHECK: liveins: $w1, $w2, $x2277 ; CHECK-NEXT: {{ $}}278 ; CHECK-NEXT: %wide_1:gpr32 = COPY $w1279 ; CHECK-NEXT: %add_lhs:gpr32sp = COPY $w2280 ; CHECK-NEXT: %res:gpr32sp = ADDWrx %add_lhs, %wide_1, 43281 ; CHECK-NEXT: $w3 = COPY %res282 ; CHECK-NEXT: RET_ReallyLR implicit $w3283 %wide_1:gpr(s32) = COPY $w1284 %1:gpr(s16) = G_TRUNC %wide_1285 %ext:gpr(s32) = G_SEXT %1(s16)286 %imm:gpr(s32) = G_CONSTANT i32 3287 %shl:gpr(s32) = G_SHL %ext, %imm288 %add_lhs:gpr(s32) = COPY $w2289 %res:gpr(s32) = G_ADD %add_lhs, %shl290 $w3 = COPY %res(s32)291 RET_ReallyLR implicit $w3292...293---294name: add_and_with_shl295alignment: 4296legalized: true297regBankSelected: true298tracksRegLiveness: true299machineFunctionInfo: {}300body: |301 bb.0:302 liveins: $w1, $w2, $x2303 ; CHECK-LABEL: name: add_and_with_shl304 ; CHECK: liveins: $w1, $w2, $x2305 ; CHECK-NEXT: {{ $}}306 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w1307 ; CHECK-NEXT: %add_lhs:gpr32sp = COPY $w2308 ; CHECK-NEXT: %res:gpr32sp = ADDWrx %add_lhs, [[COPY]], 3309 ; CHECK-NEXT: $w3 = COPY %res310 ; CHECK-NEXT: RET_ReallyLR implicit $w3311 %1:gpr(s32) = COPY $w1312 %mask:gpr(s32) = G_CONSTANT i32 255 ; 0xff313 %ext:gpr(s32) = G_AND %1(s32), %mask314 %imm:gpr(s32) = G_CONSTANT i32 3315 %shl:gpr(s32) = G_SHL %ext, %imm316 %add_lhs:gpr(s32) = COPY $w2317 %res:gpr(s32) = G_ADD %add_lhs, %shl318 $w3 = COPY %res(s32)319 RET_ReallyLR implicit $w3320...321---322name: dont_fold_invalid_mask323alignment: 4324legalized: true325regBankSelected: true326tracksRegLiveness: true327machineFunctionInfo: {}328body: |329 bb.0:330 ; Check that we only fold when we have a supported AND mask.331 liveins: $w1, $w2, $x2332 ; CHECK-LABEL: name: dont_fold_invalid_mask333 ; CHECK: liveins: $w1, $w2, $x2334 ; CHECK-NEXT: {{ $}}335 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w1336 ; CHECK-NEXT: %mask:gpr32 = MOVi32imm 42337 ; CHECK-NEXT: %ext:gpr32 = ANDWrr [[COPY]], %mask338 ; CHECK-NEXT: %add_lhs:gpr32 = COPY $w2339 ; CHECK-NEXT: %res:gpr32 = ADDWrr %add_lhs, %ext340 ; CHECK-NEXT: $w3 = COPY %res341 ; CHECK-NEXT: RET_ReallyLR implicit $w3342 %1:gpr(s32) = COPY $w1343 %mask:gpr(s32) = G_CONSTANT i32 42344 %ext:gpr(s32) = G_AND %1(s32), %mask345 %add_lhs:gpr(s32) = COPY $w2346 %res:gpr(s32) = G_ADD %add_lhs, %ext347 $w3 = COPY %res(s32)348 RET_ReallyLR implicit $w3349...350---351name: dont_fold_invalid_shl352alignment: 4353legalized: true354regBankSelected: true355tracksRegLiveness: true356machineFunctionInfo: {}357body: |358 bb.0:359 liveins: $w1, $w2, $x2360 ; CHECK-LABEL: name: dont_fold_invalid_shl361 ; CHECK: liveins: $w1, $w2, $x2362 ; CHECK-NEXT: {{ $}}363 ; CHECK-NEXT: %wide_1:gpr32 = COPY $w1364 ; CHECK-NEXT: %ext:gpr32 = SBFMWri %wide_1, 0, 15365 ; CHECK-NEXT: %add_lhs:gpr32 = COPY $w2366 ; CHECK-NEXT: %res:gpr32 = ADDWrs %add_lhs, %ext, 5367 ; CHECK-NEXT: $w3 = COPY %res368 ; CHECK-NEXT: RET_ReallyLR implicit $w3369 %wide_1:gpr(s32) = COPY $w1370 %1:gpr(s16) = G_TRUNC %wide_1371 %ext:gpr(s32) = G_SEXT %1(s16)372 %imm:gpr(s32) = G_CONSTANT i32 5373 %shl:gpr(s32) = G_SHL %ext, %imm374 %add_lhs:gpr(s32) = COPY $w2375 %res:gpr(s32) = G_ADD %add_lhs, %shl376 $w3 = COPY %res(s32)377 RET_ReallyLR implicit $w3378...379---380name: sub_sext_s32_to_s64381alignment: 4382legalized: true383regBankSelected: true384tracksRegLiveness: true385machineFunctionInfo: {}386body: |387 bb.0:388 liveins: $w1, $x2389 ; CHECK-LABEL: name: sub_sext_s32_to_s64390 ; CHECK: liveins: $w1, $x2391 ; CHECK-NEXT: {{ $}}392 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w1393 ; CHECK-NEXT: %sub_lhs:gpr64sp = COPY $x2394 ; CHECK-NEXT: %res:gpr64 = SUBSXrx %sub_lhs, [[COPY]], 48, implicit-def dead $nzcv395 ; CHECK-NEXT: $x3 = COPY %res396 ; CHECK-NEXT: RET_ReallyLR implicit $x3397 %1:gpr(s32) = COPY $w1398 %ext:gpr(s64) = G_SEXT %1(s32)399 %sub_lhs:gpr(s64) = COPY $x2400 %res:gpr(s64) = G_SUB %sub_lhs, %ext401 $x3 = COPY %res(s64)402 RET_ReallyLR implicit $x3403...404---405name: sub_sext_s16_to_s32406alignment: 4407legalized: true408regBankSelected: true409tracksRegLiveness: true410machineFunctionInfo: {}411body: |412 bb.0:413 liveins: $w1, $w2, $x2414 ; CHECK-LABEL: name: sub_sext_s16_to_s32415 ; CHECK: liveins: $w1, $w2, $x2416 ; CHECK-NEXT: {{ $}}417 ; CHECK-NEXT: %wide_1:gpr32 = COPY $w1418 ; CHECK-NEXT: %sub_lhs:gpr32sp = COPY $w2419 ; CHECK-NEXT: %res:gpr32 = SUBSWrx %sub_lhs, %wide_1, 40, implicit-def dead $nzcv420 ; CHECK-NEXT: $w3 = COPY %res421 ; CHECK-NEXT: RET_ReallyLR implicit $w3422 %wide_1:gpr(s32) = COPY $w1423 %1:gpr(s16) = G_TRUNC %wide_1424 %ext:gpr(s32) = G_SEXT %1(s16)425 %sub_lhs:gpr(s32) = COPY $w2426 %res:gpr(s32) = G_SUB %sub_lhs, %ext427 $w3 = COPY %res(s32)428 RET_ReallyLR implicit $w3429...430---431name: sub_zext_s16_to_s32432alignment: 4433legalized: true434regBankSelected: true435tracksRegLiveness: true436machineFunctionInfo: {}437body: |438 bb.0:439 liveins: $w1, $w2, $x2440 ; CHECK-LABEL: name: sub_zext_s16_to_s32441 ; CHECK: liveins: $w1, $w2, $x2442 ; CHECK-NEXT: {{ $}}443 ; CHECK-NEXT: %wide_1:gpr32 = COPY $w1444 ; CHECK-NEXT: %sub_lhs:gpr32sp = COPY $w2445 ; CHECK-NEXT: %res:gpr32 = SUBSWrx %sub_lhs, %wide_1, 8, implicit-def dead $nzcv446 ; CHECK-NEXT: $w3 = COPY %res447 ; CHECK-NEXT: RET_ReallyLR implicit $w3448 %wide_1:gpr(s32) = COPY $w1449 %1:gpr(s16) = G_TRUNC %wide_1450 %ext:gpr(s32) = G_ZEXT %1(s16)451 %sub_lhs:gpr(s32) = COPY $w2452 %res:gpr(s32) = G_SUB %sub_lhs, %ext453 $w3 = COPY %res(s32)454 RET_ReallyLR implicit $w3455...456---457name: sub_anyext_s16_to_s32458alignment: 4459legalized: true460regBankSelected: true461tracksRegLiveness: true462machineFunctionInfo: {}463body: |464 bb.0:465 liveins: $w1, $w2, $x2466 ; CHECK-LABEL: name: sub_anyext_s16_to_s32467 ; CHECK: liveins: $w1, $w2, $x2468 ; CHECK-NEXT: {{ $}}469 ; CHECK-NEXT: %wide_1:gpr32 = COPY $w1470 ; CHECK-NEXT: %sub_lhs:gpr32sp = COPY $w2471 ; CHECK-NEXT: %res:gpr32 = SUBSWrx %sub_lhs, %wide_1, 8, implicit-def dead $nzcv472 ; CHECK-NEXT: $w3 = COPY %res473 ; CHECK-NEXT: RET_ReallyLR implicit $w3474 %wide_1:gpr(s32) = COPY $w1475 %1:gpr(s16) = G_TRUNC %wide_1476 %ext:gpr(s32) = G_ANYEXT %1(s16)477 %sub_lhs:gpr(s32) = COPY $w2478 %res:gpr(s32) = G_SUB %sub_lhs, %ext479 $w3 = COPY %res(s32)480 RET_ReallyLR implicit $w3481...482---483name: sub_and_s16_to_s32_uxtb484alignment: 4485legalized: true486regBankSelected: true487tracksRegLiveness: true488machineFunctionInfo: {}489body: |490 bb.0:491 liveins: $w1, $w2, $x2492 ; CHECK-LABEL: name: sub_and_s16_to_s32_uxtb493 ; CHECK: liveins: $w1, $w2, $x2494 ; CHECK-NEXT: {{ $}}495 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w1496 ; CHECK-NEXT: %sub_lhs:gpr32sp = COPY $w2497 ; CHECK-NEXT: %res:gpr32 = SUBSWrx %sub_lhs, [[COPY]], 0, implicit-def dead $nzcv498 ; CHECK-NEXT: $w3 = COPY %res499 ; CHECK-NEXT: RET_ReallyLR implicit $w3500 %1:gpr(s32) = COPY $w1501 %mask:gpr(s32) = G_CONSTANT i32 255 ; 0xff502 %ext:gpr(s32) = G_AND %1(s32), %mask503 %sub_lhs:gpr(s32) = COPY $w2504 %res:gpr(s32) = G_SUB %sub_lhs, %ext505 $w3 = COPY %res(s32)506 RET_ReallyLR implicit $w3507...508---509name: sub_and_s16_to_s32_uxth510alignment: 4511legalized: true512regBankSelected: true513tracksRegLiveness: true514machineFunctionInfo: {}515body: |516 bb.0:517 liveins: $w1, $w2, $x2518 ; CHECK-LABEL: name: sub_and_s16_to_s32_uxth519 ; CHECK: liveins: $w1, $w2, $x2520 ; CHECK-NEXT: {{ $}}521 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w1522 ; CHECK-NEXT: %sub_lhs:gpr32sp = COPY $w2523 ; CHECK-NEXT: %res:gpr32 = SUBSWrx %sub_lhs, [[COPY]], 8, implicit-def dead $nzcv524 ; CHECK-NEXT: $w3 = COPY %res525 ; CHECK-NEXT: RET_ReallyLR implicit $w3526 %1:gpr(s32) = COPY $w1527 %mask:gpr(s32) = G_CONSTANT i32 65535 ; 0xffff528 %ext:gpr(s32) = G_AND %1(s32), %mask529 %sub_lhs:gpr(s32) = COPY $w2530 %res:gpr(s32) = G_SUB %sub_lhs, %ext531 $w3 = COPY %res(s32)532 RET_ReallyLR implicit $w3533---534name: sub_sext_s8_to_s32535alignment: 4536legalized: true537regBankSelected: true538tracksRegLiveness: true539machineFunctionInfo: {}540body: |541 bb.0:542 liveins: $w1, $w2, $x2543 %wide_1:gpr(s32) = COPY $w1544 %1:gpr(s8) = G_TRUNC %wide_1545 %ext:gpr(s32) = G_SEXT %1(s8)546 %sub_lhs:gpr(s32) = COPY $w2547 %res:gpr(s32) = G_SUB %sub_lhs, %ext548 $w3 = COPY %res(s32)549 RET_ReallyLR implicit $w3550...551---552name: sub_zext_s8_to_s32553alignment: 4554legalized: true555regBankSelected: true556tracksRegLiveness: true557machineFunctionInfo: {}558body: |559 bb.0:560 liveins: $w1, $w2, $x2561 ; CHECK-LABEL: name: sub_zext_s8_to_s32562 ; CHECK: liveins: $w1, $w2, $x2563 ; CHECK-NEXT: {{ $}}564 ; CHECK-NEXT: %wide_1:gpr32 = COPY $w1565 ; CHECK-NEXT: %sub_lhs:gpr32sp = COPY $w2566 ; CHECK-NEXT: %res:gpr32 = SUBSWrx %sub_lhs, %wide_1, 0, implicit-def dead $nzcv567 ; CHECK-NEXT: $w3 = COPY %res568 ; CHECK-NEXT: RET_ReallyLR implicit $w3569 %wide_1:gpr(s32) = COPY $w1570 %1:gpr(s8) = G_TRUNC %wide_1571 %ext:gpr(s32) = G_ZEXT %1(s8)572 %sub_lhs:gpr(s32) = COPY $w2573 %res:gpr(s32) = G_SUB %sub_lhs, %ext574 $w3 = COPY %res(s32)575 RET_ReallyLR implicit $w3576...577---578name: sub_anyext_s8_to_s32579alignment: 4580legalized: true581regBankSelected: true582tracksRegLiveness: true583machineFunctionInfo: {}584body: |585 bb.0:586 liveins: $w1, $w2, $x2587 ; CHECK-LABEL: name: sub_anyext_s8_to_s32588 ; CHECK: liveins: $w1, $w2, $x2589 ; CHECK-NEXT: {{ $}}590 ; CHECK-NEXT: %wide_1:gpr32 = COPY $w1591 ; CHECK-NEXT: %sub_lhs:gpr32sp = COPY $w2592 ; CHECK-NEXT: %res:gpr32 = SUBSWrx %sub_lhs, %wide_1, 0, implicit-def dead $nzcv593 ; CHECK-NEXT: $w3 = COPY %res594 ; CHECK-NEXT: RET_ReallyLR implicit $w3595 %wide_1:gpr(s32) = COPY $w1596 %1:gpr(s8) = G_TRUNC %wide_1597 %ext:gpr(s32) = G_ANYEXT %1(s8)598 %sub_lhs:gpr(s32) = COPY $w2599 %res:gpr(s32) = G_SUB %sub_lhs, %ext600 $w3 = COPY %res(s32)601 RET_ReallyLR implicit $w3602---603...604---605name: sub_sext_with_shl606alignment: 4607legalized: true608regBankSelected: true609tracksRegLiveness: true610machineFunctionInfo: {}611body: |612 bb.0:613 liveins: $w1, $w2, $x2614 ; CHECK-LABEL: name: sub_sext_with_shl615 ; CHECK: liveins: $w1, $w2, $x2616 ; CHECK-NEXT: {{ $}}617 ; CHECK-NEXT: %wide_1:gpr32 = COPY $w1618 ; CHECK-NEXT: %sub_lhs:gpr32sp = COPY $w2619 ; CHECK-NEXT: %res:gpr32 = SUBSWrx %sub_lhs, %wide_1, 43, implicit-def dead $nzcv620 ; CHECK-NEXT: $w3 = COPY %res621 ; CHECK-NEXT: RET_ReallyLR implicit $w3622 %wide_1:gpr(s32) = COPY $w1623 %1:gpr(s16) = G_TRUNC %wide_1624 %ext:gpr(s32) = G_SEXT %1(s16)625 %imm:gpr(s32) = G_CONSTANT i32 3626 %shl:gpr(s32) = G_SHL %ext, %imm627 %sub_lhs:gpr(s32) = COPY $w2628 %res:gpr(s32) = G_SUB %sub_lhs, %shl629 $w3 = COPY %res(s32)630 RET_ReallyLR implicit $w3631...632---633name: sub_and_with_shl634alignment: 4635legalized: true636regBankSelected: true637tracksRegLiveness: true638machineFunctionInfo: {}639body: |640 bb.0:641 liveins: $w1, $w2, $x2642 ; CHECK-LABEL: name: sub_and_with_shl643 ; CHECK: liveins: $w1, $w2, $x2644 ; CHECK-NEXT: {{ $}}645 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w1646 ; CHECK-NEXT: %sub_lhs:gpr32sp = COPY $w2647 ; CHECK-NEXT: %res:gpr32 = SUBSWrx %sub_lhs, [[COPY]], 3, implicit-def dead $nzcv648 ; CHECK-NEXT: $w3 = COPY %res649 ; CHECK-NEXT: RET_ReallyLR implicit $w3650 %1:gpr(s32) = COPY $w1651 %mask:gpr(s32) = G_CONSTANT i32 255 ; 0xff652 %ext:gpr(s32) = G_AND %1(s32), %mask653 %imm:gpr(s32) = G_CONSTANT i32 3654 %shl:gpr(s32) = G_SHL %ext, %imm655 %sub_lhs:gpr(s32) = COPY $w2656 %res:gpr(s32) = G_SUB %sub_lhs, %shl657 $w3 = COPY %res(s32)658 RET_ReallyLR implicit $w3659...660---661name: store_16b_zext662alignment: 4663legalized: true664regBankSelected: true665tracksRegLiveness: true666liveins:667 - { reg: '$x0' }668 - { reg: '$w1' }669 - { reg: '$x2' }670body: |671 bb.1.entry:672 liveins: $x0, $x1, $x2673 674 ; CHECK-LABEL: name: store_16b_zext675 ; CHECK: liveins: $x0, $x1, $x2676 ; CHECK-NEXT: {{ $}}677 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0678 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1679 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr64all = COPY $x2680 ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[COPY1]], %subreg.sub_32681 ; CHECK-NEXT: %zext:gpr64 = UBFMXri [[SUBREG_TO_REG]], 0, 15682 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:gpr64 = COPY [[COPY2]]683 ; CHECK-NEXT: STRXroX [[COPY3]], [[COPY]], %zext, 0, 1 :: (store (p0))684 ; CHECK-NEXT: RET_ReallyLR685 %0:gpr(p0) = COPY $x0686 %1:gpr(s32) = COPY $w1687 %2:gpr(p0) = COPY $x2688 %small:gpr(s16) = G_TRUNC %1689 %zext:gpr(s64) = G_ZEXT %small(s16)690 %cst:gpr(s64) = G_CONSTANT i64 3691 %shl:gpr(s64) = G_SHL %zext, %cst(s64)692 %gep:gpr(p0) = G_PTR_ADD %0, %shl(s64)693 G_STORE %2(p0), %gep(p0) :: (store (p0))694 RET_ReallyLR695...696---697name: store_8b_zext698alignment: 4699legalized: true700regBankSelected: true701tracksRegLiveness: true702liveins:703 - { reg: '$x0' }704 - { reg: '$w1' }705 - { reg: '$x2' }706body: |707 bb.1.entry:708 liveins: $x0, $x1, $x2709 710 ; CHECK-LABEL: name: store_8b_zext711 ; CHECK: liveins: $x0, $x1, $x2712 ; CHECK-NEXT: {{ $}}713 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0714 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1715 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr64all = COPY $x2716 ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[COPY1]], %subreg.sub_32717 ; CHECK-NEXT: %zext:gpr64 = UBFMXri [[SUBREG_TO_REG]], 0, 7718 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:gpr64 = COPY [[COPY2]]719 ; CHECK-NEXT: STRXroX [[COPY3]], [[COPY]], %zext, 0, 1 :: (store (p0))720 ; CHECK-NEXT: RET_ReallyLR721 %0:gpr(p0) = COPY $x0722 %1:gpr(s32) = COPY $w1723 %2:gpr(p0) = COPY $x2724 %small:gpr(s8) = G_TRUNC %1725 %zext:gpr(s64) = G_ZEXT %small(s8)726 %cst:gpr(s64) = G_CONSTANT i64 3727 %shl:gpr(s64) = G_SHL %zext, %cst(s64)728 %gep:gpr(p0) = G_PTR_ADD %0, %shl(s64)729 G_STORE %2(p0), %gep(p0) :: (store (p0))730 RET_ReallyLR731...732---733name: store_16b_sext734alignment: 4735legalized: true736regBankSelected: true737tracksRegLiveness: true738liveins:739 - { reg: '$x0' }740 - { reg: '$w1' }741 - { reg: '$x2' }742body: |743 bb.1.entry:744 liveins: $x0, $x1, $x2745 746 ; CHECK-LABEL: name: store_16b_sext747 ; CHECK: liveins: $x0, $x1, $x2748 ; CHECK-NEXT: {{ $}}749 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0750 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1751 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr64all = COPY $x2752 ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[COPY1]], %subreg.sub_32753 ; CHECK-NEXT: %zext:gpr64 = SBFMXri [[SUBREG_TO_REG]], 0, 15754 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:gpr64 = COPY [[COPY2]]755 ; CHECK-NEXT: STRXroX [[COPY3]], [[COPY]], %zext, 0, 1 :: (store (p0))756 ; CHECK-NEXT: RET_ReallyLR757 %0:gpr(p0) = COPY $x0758 %1:gpr(s32) = COPY $w1759 %2:gpr(p0) = COPY $x2760 %small:gpr(s16) = G_TRUNC %1761 %zext:gpr(s64) = G_SEXT %small(s16)762 %cst:gpr(s64) = G_CONSTANT i64 3763 %shl:gpr(s64) = G_SHL %zext, %cst(s64)764 %gep:gpr(p0) = G_PTR_ADD %0, %shl(s64)765 G_STORE %2(p0), %gep(p0) :: (store (p0))766 RET_ReallyLR767...768---769name: store_8b_sext770alignment: 4771legalized: true772regBankSelected: true773tracksRegLiveness: true774liveins:775 - { reg: '$x0' }776 - { reg: '$w1' }777 - { reg: '$x2' }778body: |779 bb.1.entry:780 liveins: $x0, $x1, $x2781 782 ; CHECK-LABEL: name: store_8b_sext783 ; CHECK: liveins: $x0, $x1, $x2784 ; CHECK-NEXT: {{ $}}785 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0786 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1787 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr64all = COPY $x2788 ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[COPY1]], %subreg.sub_32789 ; CHECK-NEXT: %zext:gpr64 = SBFMXri [[SUBREG_TO_REG]], 0, 7790 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:gpr64 = COPY [[COPY2]]791 ; CHECK-NEXT: STRXroX [[COPY3]], [[COPY]], %zext, 0, 1 :: (store (p0))792 ; CHECK-NEXT: RET_ReallyLR793 %0:gpr(p0) = COPY $x0794 %1:gpr(s32) = COPY $w1795 %2:gpr(p0) = COPY $x2796 %small:gpr(s8) = G_TRUNC %1797 %zext:gpr(s64) = G_SEXT %small(s8)798 %cst:gpr(s64) = G_CONSTANT i64 3799 %shl:gpr(s64) = G_SHL %zext, %cst(s64)800 %gep:gpr(p0) = G_PTR_ADD %0, %shl(s64)801 G_STORE %2(p0), %gep(p0) :: (store (p0))802 RET_ReallyLR803...804