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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=aarch64-unknown-unknown -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s3 4---5name: add_shl_s64_rhs6legalized: true7regBankSelected: true8tracksRegLiveness: true9body: |10 bb.0:11 liveins: $x012 ; CHECK-LABEL: name: add_shl_s64_rhs13 ; CHECK: liveins: $x014 ; CHECK-NEXT: {{ $}}15 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x016 ; CHECK-NEXT: [[ADDXrs:%[0-9]+]]:gpr64 = ADDXrs [[COPY]], [[COPY]], 817 ; CHECK-NEXT: $x0 = COPY [[ADDXrs]]18 ; CHECK-NEXT: RET_ReallyLR implicit $x019 %0:gpr(s64) = COPY $x020 %1:gpr(s64) = G_CONSTANT i64 821 %2:gpr(s64) = G_SHL %0, %1:gpr(s64)22 %3:gpr(s64) = G_ADD %0, %2:gpr(s64)23 $x0 = COPY %3:gpr(s64)24 RET_ReallyLR implicit $x025 26...27---28name: add_shl_s64_lhs29legalized: true30regBankSelected: true31tracksRegLiveness: true32body: |33 bb.0:34 liveins: $x0, $x135 ; CHECK-LABEL: name: add_shl_s64_lhs36 ; CHECK: liveins: $x0, $x137 ; CHECK-NEXT: {{ $}}38 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x039 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64 = COPY $x140 ; CHECK-NEXT: [[ADDXrs:%[0-9]+]]:gpr64 = ADDXrs [[COPY1]], [[COPY]], 841 ; CHECK-NEXT: $x0 = COPY [[ADDXrs]]42 ; CHECK-NEXT: RET_ReallyLR implicit $x043 %0:gpr(s64) = COPY $x044 %4:gpr(s64) = COPY $x145 %1:gpr(s64) = G_CONSTANT i64 846 %2:gpr(s64) = G_SHL %0, %1:gpr(s64)47 %3:gpr(s64) = G_ADD %2, %4:gpr(s64)48 $x0 = COPY %3:gpr(s64)49 RET_ReallyLR implicit $x050 51...52---53name: sub_shl_s64_rhs54legalized: true55regBankSelected: true56tracksRegLiveness: true57body: |58 bb.0:59 liveins: $x060 ; CHECK-LABEL: name: sub_shl_s64_rhs61 ; CHECK: liveins: $x062 ; CHECK-NEXT: {{ $}}63 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x064 ; CHECK-NEXT: [[SUBSXrs:%[0-9]+]]:gpr64 = SUBSXrs [[COPY]], [[COPY]], 8, implicit-def dead $nzcv65 ; CHECK-NEXT: $x0 = COPY [[SUBSXrs]]66 ; CHECK-NEXT: RET_ReallyLR implicit $x067 %0:gpr(s64) = COPY $x068 %1:gpr(s64) = G_CONSTANT i64 869 %2:gpr(s64) = G_SHL %0, %1:gpr(s64)70 %3:gpr(s64) = G_SUB %0, %2:gpr(s64)71 $x0 = COPY %3:gpr(s64)72 RET_ReallyLR implicit $x073 74---75name: add_lshr_s64_rhs76legalized: true77regBankSelected: true78tracksRegLiveness: true79body: |80 bb.0:81 liveins: $x082 %0:gpr(s64) = COPY $x083 %1:gpr(s64) = G_CONSTANT i64 884 %2:gpr(s64) = G_LSHR %0, %1:gpr(s64)85 %3:gpr(s64) = G_ADD %0, %2:gpr(s64)86 $x0 = COPY %3:gpr(s64)87 RET_ReallyLR implicit $x088 89...90---91name: add_lshr_s64_lhs92legalized: true93regBankSelected: true94tracksRegLiveness: true95body: |96 bb.0:97 liveins: $x0, $x198 ; CHECK-LABEL: name: add_lshr_s64_lhs99 ; CHECK: liveins: $x0, $x1100 ; CHECK-NEXT: {{ $}}101 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0102 ; CHECK-NEXT: %param2:gpr64 = COPY $x1103 ; CHECK-NEXT: [[ADDXrs:%[0-9]+]]:gpr64 = ADDXrs %param2, [[COPY]], 72104 ; CHECK-NEXT: $x0 = COPY [[ADDXrs]]105 ; CHECK-NEXT: RET_ReallyLR implicit $x0106 %0:gpr(s64) = COPY $x0107 %param2:gpr(s64) = COPY $x1108 %1:gpr(s64) = G_CONSTANT i64 8109 %2:gpr(s64) = G_LSHR %0, %1:gpr(s64)110 %3:gpr(s64) = G_ADD %2, %param2:gpr(s64)111 $x0 = COPY %3:gpr(s64)112 RET_ReallyLR implicit $x0113 114...115---116name: sub_lshr_s64_rhs117legalized: true118regBankSelected: true119tracksRegLiveness: true120body: |121 bb.0:122 liveins: $x0123 ; CHECK-LABEL: name: sub_lshr_s64_rhs124 ; CHECK: liveins: $x0125 ; CHECK-NEXT: {{ $}}126 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0127 ; CHECK-NEXT: [[SUBSXrs:%[0-9]+]]:gpr64 = SUBSXrs [[COPY]], [[COPY]], 72, implicit-def dead $nzcv128 ; CHECK-NEXT: $x0 = COPY [[SUBSXrs]]129 ; CHECK-NEXT: RET_ReallyLR implicit $x0130 %0:gpr(s64) = COPY $x0131 %1:gpr(s64) = G_CONSTANT i64 8132 %2:gpr(s64) = G_LSHR %0, %1:gpr(s64)133 %3:gpr(s64) = G_SUB %0, %2:gpr(s64)134 $x0 = COPY %3:gpr(s64)135 RET_ReallyLR implicit $x0136 137...138---139name: add_ashr_s64_rhs140legalized: true141regBankSelected: true142tracksRegLiveness: true143body: |144 bb.0:145 liveins: $x0146 ; CHECK-LABEL: name: add_ashr_s64_rhs147 ; CHECK: liveins: $x0148 ; CHECK-NEXT: {{ $}}149 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0150 ; CHECK-NEXT: [[ADDXrs:%[0-9]+]]:gpr64 = ADDXrs [[COPY]], [[COPY]], 136151 ; CHECK-NEXT: $x0 = COPY [[ADDXrs]]152 ; CHECK-NEXT: RET_ReallyLR implicit $x0153 %0:gpr(s64) = COPY $x0154 %1:gpr(s64) = G_CONSTANT i64 8155 %2:gpr(s64) = G_ASHR %0, %1:gpr(s64)156 %3:gpr(s64) = G_ADD %0, %2:gpr(s64)157 $x0 = COPY %3:gpr(s64)158 RET_ReallyLR implicit $x0159 160...161---162name: add_ashr_s64_lhs163legalized: true164regBankSelected: true165tracksRegLiveness: true166body: |167 bb.0:168 liveins: $x0, $x1169 ; CHECK-LABEL: name: add_ashr_s64_lhs170 ; CHECK: liveins: $x0, $x1171 ; CHECK-NEXT: {{ $}}172 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0173 ; CHECK-NEXT: %param2:gpr64 = COPY $x1174 ; CHECK-NEXT: [[ADDXrs:%[0-9]+]]:gpr64 = ADDXrs %param2, [[COPY]], 136175 ; CHECK-NEXT: $x0 = COPY [[ADDXrs]]176 ; CHECK-NEXT: RET_ReallyLR implicit $x0177 %0:gpr(s64) = COPY $x0178 %param2:gpr(s64) = COPY $x1179 %1:gpr(s64) = G_CONSTANT i64 8180 %2:gpr(s64) = G_ASHR %0, %1:gpr(s64)181 %3:gpr(s64) = G_ADD %2, %param2:gpr(s64)182 $x0 = COPY %3:gpr(s64)183 RET_ReallyLR implicit $x0184 185...186---187name: sub_ashr_s64_rhs188legalized: true189regBankSelected: true190tracksRegLiveness: true191body: |192 bb.0:193 liveins: $x0194 ; CHECK-LABEL: name: sub_ashr_s64_rhs195 ; CHECK: liveins: $x0196 ; CHECK-NEXT: {{ $}}197 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0198 ; CHECK-NEXT: [[SUBSXrs:%[0-9]+]]:gpr64 = SUBSXrs [[COPY]], [[COPY]], 136, implicit-def dead $nzcv199 ; CHECK-NEXT: $x0 = COPY [[SUBSXrs]]200 ; CHECK-NEXT: RET_ReallyLR implicit $x0201 %0:gpr(s64) = COPY $x0202 %1:gpr(s64) = G_CONSTANT i64 8203 %2:gpr(s64) = G_ASHR %0, %1:gpr(s64)204 %3:gpr(s64) = G_SUB %0, %2:gpr(s64)205 $x0 = COPY %3:gpr(s64)206 RET_ReallyLR implicit $x0207 208---209name: add_shl_s32_rhs210legalized: true211regBankSelected: true212tracksRegLiveness: true213body: |214 bb.0:215 liveins: $w0216 %0:gpr(s32) = COPY $w0217 %1:gpr(s32) = G_CONSTANT i32 8218 %2:gpr(s32) = G_SHL %0, %1:gpr(s32)219 %3:gpr(s32) = G_ADD %0, %2:gpr(s32)220 $w0 = COPY %3:gpr(s32)221 RET_ReallyLR implicit $w0222 223...224---225name: add_shl_s32_lhs226legalized: true227regBankSelected: true228tracksRegLiveness: true229body: |230 bb.0:231 liveins: $w0, $w1232 ; CHECK-LABEL: name: add_shl_s32_lhs233 ; CHECK: liveins: $w0, $w1234 ; CHECK-NEXT: {{ $}}235 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0236 ; CHECK-NEXT: %param2:gpr32 = COPY $w1237 ; CHECK-NEXT: [[ADDWrs:%[0-9]+]]:gpr32 = ADDWrs %param2, [[COPY]], 8238 ; CHECK-NEXT: $w0 = COPY [[ADDWrs]]239 ; CHECK-NEXT: RET_ReallyLR implicit $w0240 %0:gpr(s32) = COPY $w0241 %param2:gpr(s32) = COPY $w1242 %1:gpr(s32) = G_CONSTANT i32 8243 %2:gpr(s32) = G_SHL %0, %1:gpr(s32)244 %3:gpr(s32) = G_ADD %2, %param2:gpr(s32)245 $w0 = COPY %3:gpr(s32)246 RET_ReallyLR implicit $w0247 248...249---250name: sub_shl_s32_rhs251legalized: true252regBankSelected: true253tracksRegLiveness: true254body: |255 bb.0:256 liveins: $w0257 ; CHECK-LABEL: name: sub_shl_s32_rhs258 ; CHECK: liveins: $w0259 ; CHECK-NEXT: {{ $}}260 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0261 ; CHECK-NEXT: [[SUBSWrs:%[0-9]+]]:gpr32 = SUBSWrs [[COPY]], [[COPY]], 8, implicit-def dead $nzcv262 ; CHECK-NEXT: $w0 = COPY [[SUBSWrs]]263 ; CHECK-NEXT: RET_ReallyLR implicit $w0264 %0:gpr(s32) = COPY $w0265 %1:gpr(s32) = G_CONSTANT i32 8266 %2:gpr(s32) = G_SHL %0, %1:gpr(s32)267 %3:gpr(s32) = G_SUB %0, %2:gpr(s32)268 $w0 = COPY %3:gpr(s32)269 RET_ReallyLR implicit $w0270 271...272---273name: add_lshr_s32_rhs274legalized: true275regBankSelected: true276tracksRegLiveness: true277body: |278 bb.0:279 liveins: $w0280 ; CHECK-LABEL: name: add_lshr_s32_rhs281 ; CHECK: liveins: $w0282 ; CHECK-NEXT: {{ $}}283 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0284 ; CHECK-NEXT: [[ADDWrs:%[0-9]+]]:gpr32 = ADDWrs [[COPY]], [[COPY]], 72285 ; CHECK-NEXT: $w0 = COPY [[ADDWrs]]286 ; CHECK-NEXT: RET_ReallyLR implicit $w0287 %0:gpr(s32) = COPY $w0288 %1:gpr(s32) = G_CONSTANT i32 8289 %2:gpr(s32) = G_LSHR %0, %1:gpr(s32)290 %3:gpr(s32) = G_ADD %0, %2:gpr(s32)291 $w0 = COPY %3:gpr(s32)292 RET_ReallyLR implicit $w0293 294...295---296name: add_lshr_s32_lhs297legalized: true298regBankSelected: true299tracksRegLiveness: true300body: |301 bb.0:302 liveins: $w0, $w1303 ; CHECK-LABEL: name: add_lshr_s32_lhs304 ; CHECK: liveins: $w0, $w1305 ; CHECK-NEXT: {{ $}}306 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0307 ; CHECK-NEXT: %param2:gpr32 = COPY $w1308 ; CHECK-NEXT: [[ADDWrs:%[0-9]+]]:gpr32 = ADDWrs %param2, [[COPY]], 72309 ; CHECK-NEXT: $w0 = COPY [[ADDWrs]]310 ; CHECK-NEXT: RET_ReallyLR implicit $w0311 %0:gpr(s32) = COPY $w0312 %param2:gpr(s32) = COPY $w1313 %1:gpr(s32) = G_CONSTANT i32 8314 %2:gpr(s32) = G_LSHR %0, %1:gpr(s32)315 %3:gpr(s32) = G_ADD %2, %param2:gpr(s32)316 $w0 = COPY %3:gpr(s32)317 RET_ReallyLR implicit $w0318 319...320---321name: sub_lshr_s32_rhs322legalized: true323regBankSelected: true324tracksRegLiveness: true325body: |326 bb.0:327 liveins: $w0328 ; CHECK-LABEL: name: sub_lshr_s32_rhs329 ; CHECK: liveins: $w0330 ; CHECK-NEXT: {{ $}}331 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0332 ; CHECK-NEXT: [[SUBSWrs:%[0-9]+]]:gpr32 = SUBSWrs [[COPY]], [[COPY]], 72, implicit-def dead $nzcv333 ; CHECK-NEXT: $w0 = COPY [[SUBSWrs]]334 ; CHECK-NEXT: RET_ReallyLR implicit $w0335 %0:gpr(s32) = COPY $w0336 %1:gpr(s32) = G_CONSTANT i32 8337 %2:gpr(s32) = G_LSHR %0, %1:gpr(s32)338 %3:gpr(s32) = G_SUB %0, %2:gpr(s32)339 $w0 = COPY %3:gpr(s32)340 RET_ReallyLR implicit $w0341 342...343---344name: add_ashr_s32_rhs345legalized: true346regBankSelected: true347tracksRegLiveness: true348body: |349 bb.0:350 liveins: $w0351 ; CHECK-LABEL: name: add_ashr_s32_rhs352 ; CHECK: liveins: $w0353 ; CHECK-NEXT: {{ $}}354 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0355 ; CHECK-NEXT: [[ADDWrs:%[0-9]+]]:gpr32 = ADDWrs [[COPY]], [[COPY]], 136356 ; CHECK-NEXT: $w0 = COPY [[ADDWrs]]357 ; CHECK-NEXT: RET_ReallyLR implicit $w0358 %0:gpr(s32) = COPY $w0359 %1:gpr(s32) = G_CONSTANT i32 8360 %2:gpr(s32) = G_ASHR %0, %1:gpr(s32)361 %3:gpr(s32) = G_ADD %0, %2:gpr(s32)362 $w0 = COPY %3:gpr(s32)363 RET_ReallyLR implicit $w0364 365...366---367name: add_ashr_s32_lhs368legalized: true369regBankSelected: true370tracksRegLiveness: true371body: |372 bb.0:373 liveins: $w0, $w1374 ; CHECK-LABEL: name: add_ashr_s32_lhs375 ; CHECK: liveins: $w0, $w1376 ; CHECK-NEXT: {{ $}}377 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0378 ; CHECK-NEXT: %param2:gpr32 = COPY $w1379 ; CHECK-NEXT: [[ADDWrs:%[0-9]+]]:gpr32 = ADDWrs %param2, [[COPY]], 136380 ; CHECK-NEXT: $w0 = COPY [[ADDWrs]]381 ; CHECK-NEXT: RET_ReallyLR implicit $w0382 %0:gpr(s32) = COPY $w0383 %param2:gpr(s32) = COPY $w1384 %1:gpr(s32) = G_CONSTANT i32 8385 %2:gpr(s32) = G_ASHR %0, %1:gpr(s32)386 %3:gpr(s32) = G_ADD %2, %param2:gpr(s32)387 $w0 = COPY %3:gpr(s32)388 RET_ReallyLR implicit $w0389 390...391---392name: sub_ashr_s32_rhs393legalized: true394regBankSelected: true395tracksRegLiveness: true396body: |397 bb.0:398 liveins: $w0399 ; CHECK-LABEL: name: sub_ashr_s32_rhs400 ; CHECK: liveins: $w0401 ; CHECK-NEXT: {{ $}}402 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0403 ; CHECK-NEXT: [[SUBSWrs:%[0-9]+]]:gpr32 = SUBSWrs [[COPY]], [[COPY]], 136, implicit-def dead $nzcv404 ; CHECK-NEXT: $w0 = COPY [[SUBSWrs]]405 ; CHECK-NEXT: RET_ReallyLR implicit $w0406 %0:gpr(s32) = COPY $w0407 %1:gpr(s32) = G_CONSTANT i32 8408 %2:gpr(s32) = G_ASHR %0, %1:gpr(s32)409 %3:gpr(s32) = G_SUB %0, %2:gpr(s32)410 $w0 = COPY %3:gpr(s32)411 RET_ReallyLR implicit $w0412