263 lines · plain
1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=aarch64-- -mattr=+lse -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s3 4--- |5 target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"6 7 define void @atomicrmw_xchg_i64(ptr %addr) { ret void }8 define void @atomicrmw_add_i64(ptr %addr) { ret void }9 define void @atomicrmw_add_i32(ptr %addr) { ret void }10 define void @atomicrmw_sub_i32(ptr %addr) { ret void }11 define void @atomicrmw_and_i32(ptr %addr) { ret void }12 ; nand isn't legal13 define void @atomicrmw_or_i32(ptr %addr) { ret void }14 define void @atomicrmw_xor_i32(ptr %addr) { ret void }15 define void @atomicrmw_min_i32(ptr %addr) { ret void }16 define void @atomicrmw_max_i32(ptr %addr) { ret void }17 define void @atomicrmw_umin_i32(ptr %addr) { ret void }18 define void @atomicrmw_umax_i32(ptr %addr) { ret void }19...20 21---22name: atomicrmw_xchg_i6423legalized: true24regBankSelected: true25 26body: |27 bb.0:28 liveins: $x029 30 ; CHECK-LABEL: name: atomicrmw_xchg_i6431 ; CHECK: liveins: $x032 ; CHECK-NEXT: {{ $}}33 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x034 ; CHECK-NEXT: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 135 ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[MOVi32imm]], %subreg.sub_3236 ; CHECK-NEXT: [[SWPX:%[0-9]+]]:gpr64 = SWPX [[SUBREG_TO_REG]], [[COPY]] :: (load store monotonic (s64) on %ir.addr)37 ; CHECK-NEXT: $x0 = COPY [[SWPX]]38 %0:gpr(p0) = COPY $x039 %1:gpr(s64) = G_CONSTANT i64 140 %2:gpr(s64) = G_ATOMICRMW_XCHG %0, %1 :: (load store monotonic (s64) on %ir.addr)41 $x0 = COPY %2(s64)42...43---44name: atomicrmw_add_i6445legalized: true46regBankSelected: true47 48body: |49 bb.0:50 liveins: $x051 52 ; CHECK-LABEL: name: atomicrmw_add_i6453 ; CHECK: liveins: $x054 ; CHECK-NEXT: {{ $}}55 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x056 ; CHECK-NEXT: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 157 ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[MOVi32imm]], %subreg.sub_3258 ; CHECK-NEXT: [[LDADDX:%[0-9]+]]:gpr64 = LDADDX [[SUBREG_TO_REG]], [[COPY]] :: (load store monotonic (s64) on %ir.addr)59 ; CHECK-NEXT: $x0 = COPY [[LDADDX]]60 %0:gpr(p0) = COPY $x061 %1:gpr(s64) = G_CONSTANT i64 162 %2:gpr(s64) = G_ATOMICRMW_ADD %0, %1 :: (load store monotonic (s64) on %ir.addr)63 $x0 = COPY %2(s64)64...65---66name: atomicrmw_add_i3267legalized: true68regBankSelected: true69 70body: |71 bb.0:72 liveins: $x073 74 ; CHECK-LABEL: name: atomicrmw_add_i3275 ; CHECK: liveins: $x076 ; CHECK-NEXT: {{ $}}77 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x078 ; CHECK-NEXT: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 179 ; CHECK-NEXT: [[LDADDALW:%[0-9]+]]:gpr32 = LDADDALW [[MOVi32imm]], [[COPY]] :: (load store seq_cst (s32) on %ir.addr)80 ; CHECK-NEXT: $w0 = COPY [[LDADDALW]]81 %0:gpr(p0) = COPY $x082 %1:gpr(s32) = G_CONSTANT i32 183 %2:gpr(s32) = G_ATOMICRMW_ADD %0, %1 :: (load store seq_cst (s32) on %ir.addr)84 $w0 = COPY %2(s32)85...86 87---88name: atomicrmw_sub_i3289legalized: true90regBankSelected: true91 92body: |93 bb.0:94 liveins: $x095 96 ; CHECK-LABEL: name: atomicrmw_sub_i3297 ; CHECK: liveins: $x098 ; CHECK-NEXT: {{ $}}99 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0100 ; CHECK-NEXT: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1101 ; CHECK-NEXT: [[LDADDALW:%[0-9]+]]:gpr32 = LDADDALW [[MOVi32imm]], [[COPY]] :: (load store seq_cst (s32) on %ir.addr)102 ; CHECK-NEXT: $w0 = COPY [[LDADDALW]]103 %0:gpr(p0) = COPY $x0104 %1:gpr(s32) = G_CONSTANT i32 1105 %2:gpr(s32) = G_ATOMICRMW_ADD %0, %1 :: (load store seq_cst (s32) on %ir.addr)106 $w0 = COPY %2(s32)107...108 109---110name: atomicrmw_and_i32111legalized: true112regBankSelected: true113 114body: |115 bb.0:116 liveins: $x0117 118 ; CHECK-LABEL: name: atomicrmw_and_i32119 ; CHECK: liveins: $x0120 ; CHECK-NEXT: {{ $}}121 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0122 ; CHECK-NEXT: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1123 ; CHECK-NEXT: [[ORNWrr:%[0-9]+]]:gpr32 = ORNWrr $wzr, [[MOVi32imm]]124 ; CHECK-NEXT: [[LDCLRAW:%[0-9]+]]:gpr32 = LDCLRAW [[ORNWrr]], [[COPY]] :: (load store acquire (s32) on %ir.addr)125 ; CHECK-NEXT: $w0 = COPY [[LDCLRAW]]126 %0:gpr(p0) = COPY $x0127 %1:gpr(s32) = G_CONSTANT i32 1128 %2:gpr(s32) = G_ATOMICRMW_AND %0, %1 :: (load store acquire (s32) on %ir.addr)129 $w0 = COPY %2(s32)130...131 132---133name: atomicrmw_or_i32134legalized: true135regBankSelected: true136 137body: |138 bb.0:139 liveins: $x0140 141 ; CHECK-LABEL: name: atomicrmw_or_i32142 ; CHECK: liveins: $x0143 ; CHECK-NEXT: {{ $}}144 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0145 ; CHECK-NEXT: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1146 ; CHECK-NEXT: [[LDSETLW:%[0-9]+]]:gpr32 = LDSETLW [[MOVi32imm]], [[COPY]] :: (load store release (s32) on %ir.addr)147 ; CHECK-NEXT: $w0 = COPY [[LDSETLW]]148 %0:gpr(p0) = COPY $x0149 %1:gpr(s32) = G_CONSTANT i32 1150 %2:gpr(s32) = G_ATOMICRMW_OR %0, %1 :: (load store release (s32) on %ir.addr)151 $w0 = COPY %2(s32)152...153 154---155name: atomicrmw_xor_i32156legalized: true157regBankSelected: true158 159body: |160 bb.0:161 liveins: $x0162 163 ; CHECK-LABEL: name: atomicrmw_xor_i32164 ; CHECK: liveins: $x0165 ; CHECK-NEXT: {{ $}}166 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0167 ; CHECK-NEXT: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1168 ; CHECK-NEXT: [[LDEORALW:%[0-9]+]]:gpr32 = LDEORALW [[MOVi32imm]], [[COPY]] :: (load store acq_rel (s32) on %ir.addr)169 ; CHECK-NEXT: $w0 = COPY [[LDEORALW]]170 %0:gpr(p0) = COPY $x0171 %1:gpr(s32) = G_CONSTANT i32 1172 %2:gpr(s32) = G_ATOMICRMW_XOR %0, %1 :: (load store acq_rel (s32) on %ir.addr)173 $w0 = COPY %2(s32)174...175 176---177name: atomicrmw_min_i32178legalized: true179regBankSelected: true180 181body: |182 bb.0:183 liveins: $x0184 185 ; CHECK-LABEL: name: atomicrmw_min_i32186 ; CHECK: liveins: $x0187 ; CHECK-NEXT: {{ $}}188 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0189 ; CHECK-NEXT: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1190 ; CHECK-NEXT: [[LDSMINALW:%[0-9]+]]:gpr32 = LDSMINALW [[MOVi32imm]], [[COPY]] :: (load store acq_rel (s32) on %ir.addr)191 ; CHECK-NEXT: $w0 = COPY [[LDSMINALW]]192 %0:gpr(p0) = COPY $x0193 %1:gpr(s32) = G_CONSTANT i32 1194 %2:gpr(s32) = G_ATOMICRMW_MIN %0, %1 :: (load store acq_rel (s32) on %ir.addr)195 $w0 = COPY %2(s32)196...197 198---199name: atomicrmw_max_i32200legalized: true201regBankSelected: true202 203body: |204 bb.0:205 liveins: $x0206 207 ; CHECK-LABEL: name: atomicrmw_max_i32208 ; CHECK: liveins: $x0209 ; CHECK-NEXT: {{ $}}210 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0211 ; CHECK-NEXT: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1212 ; CHECK-NEXT: [[LDSMAXALW:%[0-9]+]]:gpr32 = LDSMAXALW [[MOVi32imm]], [[COPY]] :: (load store acq_rel (s32) on %ir.addr)213 ; CHECK-NEXT: $w0 = COPY [[LDSMAXALW]]214 %0:gpr(p0) = COPY $x0215 %1:gpr(s32) = G_CONSTANT i32 1216 %2:gpr(s32) = G_ATOMICRMW_MAX %0, %1 :: (load store acq_rel (s32) on %ir.addr)217 $w0 = COPY %2(s32)218...219 220---221name: atomicrmw_umin_i32222legalized: true223regBankSelected: true224 225body: |226 bb.0:227 liveins: $x0228 229 ; CHECK-LABEL: name: atomicrmw_umin_i32230 ; CHECK: liveins: $x0231 ; CHECK-NEXT: {{ $}}232 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0233 ; CHECK-NEXT: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1234 ; CHECK-NEXT: [[LDUMINALW:%[0-9]+]]:gpr32 = LDUMINALW [[MOVi32imm]], [[COPY]] :: (load store acq_rel (s32) on %ir.addr)235 ; CHECK-NEXT: $w0 = COPY [[LDUMINALW]]236 %0:gpr(p0) = COPY $x0237 %1:gpr(s32) = G_CONSTANT i32 1238 %2:gpr(s32) = G_ATOMICRMW_UMIN %0, %1 :: (load store acq_rel (s32) on %ir.addr)239 $w0 = COPY %2(s32)240...241 242---243name: atomicrmw_umax_i32244legalized: true245regBankSelected: true246 247body: |248 bb.0:249 liveins: $x0250 251 ; CHECK-LABEL: name: atomicrmw_umax_i32252 ; CHECK: liveins: $x0253 ; CHECK-NEXT: {{ $}}254 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0255 ; CHECK-NEXT: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1256 ; CHECK-NEXT: [[LDUMAXALW:%[0-9]+]]:gpr32 = LDUMAXALW [[MOVi32imm]], [[COPY]] :: (load store acq_rel (s32) on %ir.addr)257 ; CHECK-NEXT: $w0 = COPY [[LDUMAXALW]]258 %0:gpr(p0) = COPY $x0259 %1:gpr(s32) = G_CONSTANT i32 1260 %2:gpr(s32) = G_ATOMICRMW_UMAX %0, %1 :: (load store acq_rel (s32) on %ir.addr)261 $w0 = COPY %2(s32)262...263