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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s3---4# Check that we select a 32-bit GPR G_ADD into ADDWrr on GPR32.5# Also check that we constrain the register class of the COPY to GPR32.6name: add_s32_gpr7legalized: true8regBankSelected: true9 10registers:11 - { id: 0, class: gpr }12 - { id: 1, class: gpr }13 - { id: 2, class: gpr }14 15body: |16 bb.0:17 liveins: $w0, $w118 19 ; CHECK-LABEL: name: add_s32_gpr20 ; CHECK: liveins: $w0, $w121 ; CHECK-NEXT: {{ $}}22 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w023 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w124 ; CHECK-NEXT: [[ADDWrr:%[0-9]+]]:gpr32 = ADDWrr [[COPY]], [[COPY1]]25 ; CHECK-NEXT: $w0 = COPY [[ADDWrr]]26 %0(s32) = COPY $w027 %1(s32) = COPY $w128 %2(s32) = G_ADD %0, %129 $w0 = COPY %2(s32)30...31 32---33# Same as add_s32_gpr, for 64-bit operations.34name: add_s64_gpr35legalized: true36regBankSelected: true37 38registers:39 - { id: 0, class: gpr }40 - { id: 1, class: gpr }41 - { id: 2, class: gpr }42 43body: |44 bb.0:45 liveins: $x0, $x146 47 ; CHECK-LABEL: name: add_s64_gpr48 ; CHECK: liveins: $x0, $x149 ; CHECK-NEXT: {{ $}}50 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x051 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64 = COPY $x152 ; CHECK-NEXT: [[ADDXrr:%[0-9]+]]:gpr64 = ADDXrr [[COPY]], [[COPY1]]53 ; CHECK-NEXT: $x0 = COPY [[ADDXrr]]54 %0(s64) = COPY $x055 %1(s64) = COPY $x156 %2(s64) = G_ADD %0, %157 $x0 = COPY %2(s64)58...59 60---61name: add_imm_s32_gpr62legalized: true63regBankSelected: true64 65registers:66 - { id: 0, class: gpr }67 - { id: 1, class: gpr }68 - { id: 2, class: gpr }69 70body: |71 bb.0:72 liveins: $w0, $w173 74 ; CHECK-LABEL: name: add_imm_s32_gpr75 ; CHECK: liveins: $w0, $w176 ; CHECK-NEXT: {{ $}}77 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32sp = COPY $w078 ; CHECK-NEXT: [[ADDWri:%[0-9]+]]:gpr32sp = ADDWri [[COPY]], 1, 079 ; CHECK-NEXT: $w0 = COPY [[ADDWri]]80 %0(s32) = COPY $w081 %1(s32) = G_CONSTANT i32 182 %2(s32) = G_ADD %0, %183 $w0 = COPY %2(s32)84...85 86---87name: add_imm_s64_gpr88legalized: true89regBankSelected: true90 91registers:92 - { id: 0, class: gpr }93 - { id: 1, class: gpr }94 - { id: 2, class: gpr }95 96body: |97 bb.0:98 liveins: $x0, $w199 100 ; CHECK-LABEL: name: add_imm_s64_gpr101 ; CHECK: liveins: $x0, $w1102 ; CHECK-NEXT: {{ $}}103 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0104 ; CHECK-NEXT: [[ADDXri:%[0-9]+]]:gpr64sp = ADDXri [[COPY]], 1, 0105 ; CHECK-NEXT: $x0 = COPY [[ADDXri]]106 %0(s64) = COPY $x0107 %1(s64) = G_CONSTANT i64 1108 %2(s64) = G_ADD %0, %1109 $x0 = COPY %2(s64)110...111 112---113name: add_neg_s32_gpr114legalized: true115regBankSelected: true116 117registers:118 - { id: 0, class: gpr }119 - { id: 1, class: gpr }120 - { id: 2, class: gpr }121 122body: |123 bb.0:124 liveins: $w1, $w2125 ; We should be able to turn the ADD into a SUB.126 ; CHECK-LABEL: name: add_neg_s32_gpr127 ; CHECK: liveins: $w1, $w2128 ; CHECK-NEXT: {{ $}}129 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32sp = COPY $w1130 ; CHECK-NEXT: [[SUBSWri:%[0-9]+]]:gpr32 = SUBSWri [[COPY]], 1, 0, implicit-def dead $nzcv131 ; CHECK-NEXT: $w2 = COPY [[SUBSWri]]132 %0(s32) = COPY $w1133 %1(s32) = G_CONSTANT i32 -1134 %2(s32) = G_ADD %0, %1135 $w2 = COPY %2(s32)136...137 138---139name: add_neg_s64_gpr140legalized: true141regBankSelected: true142 143registers:144 - { id: 0, class: gpr }145 - { id: 1, class: gpr }146 - { id: 2, class: gpr }147 148body: |149 bb.0:150 liveins: $x0, $x1151 ; We should be able to turn the ADD into a SUB.152 ; CHECK-LABEL: name: add_neg_s64_gpr153 ; CHECK: liveins: $x0, $x1154 ; CHECK-NEXT: {{ $}}155 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0156 ; CHECK-NEXT: [[SUBSXri:%[0-9]+]]:gpr64 = SUBSXri [[COPY]], 1, 0, implicit-def dead $nzcv157 ; CHECK-NEXT: $x0 = COPY [[SUBSXri]]158 %0(s64) = COPY $x0159 %1(s64) = G_CONSTANT i64 -1160 %2(s64) = G_ADD %0, %1161 $x0 = COPY %2(s64)162...163 164---165name: add_neg_invalid_immed_s32166legalized: true167regBankSelected: true168 169registers:170 - { id: 0, class: gpr }171 - { id: 1, class: gpr }172 - { id: 2, class: gpr }173 174body: |175 bb.0:176 liveins: $x0, $x1177 ; We can't select this if the value is out of range.178 ; CHECK-LABEL: name: add_neg_invalid_immed_s32179 ; CHECK: liveins: $x0, $x1180 ; CHECK-NEXT: {{ $}}181 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0182 ; CHECK-NEXT: [[MOVi64imm:%[0-9]+]]:gpr64 = MOVi64imm -5000183 ; CHECK-NEXT: [[ADDXrr:%[0-9]+]]:gpr64 = ADDXrr [[COPY]], [[MOVi64imm]]184 ; CHECK-NEXT: $x0 = COPY [[ADDXrr]]185 %0(s64) = COPY $x0186 %1(s64) = G_CONSTANT i64 -5000187 %2(s64) = G_ADD %0, %1188 $x0 = COPY %2(s64)189...190 191---192name: add_neg_invalid_immed_s64193legalized: true194regBankSelected: true195 196registers:197 - { id: 0, class: gpr }198 - { id: 1, class: gpr }199 - { id: 2, class: gpr }200 201body: |202 bb.0:203 liveins: $x0, $x1204 ; We can't select this if the value is out of range.205 ; CHECK-LABEL: name: add_neg_invalid_immed_s64206 ; CHECK: liveins: $x0, $x1207 ; CHECK-NEXT: {{ $}}208 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0209 ; CHECK-NEXT: [[MOVi64imm:%[0-9]+]]:gpr64 = MOVi64imm -5000210 ; CHECK-NEXT: [[ADDXrr:%[0-9]+]]:gpr64 = ADDXrr [[COPY]], [[MOVi64imm]]211 ; CHECK-NEXT: $x0 = COPY [[ADDXrr]]212 %0(s64) = COPY $x0213 %1(s64) = G_CONSTANT i64 -5000214 %2(s64) = G_ADD %0, %1215 $x0 = COPY %2(s64)216...217 218---219name: add_imm_0_s32220legalized: true221regBankSelected: true222 223registers:224 - { id: 0, class: gpr }225 - { id: 1, class: gpr }226 - { id: 2, class: gpr }227 228body: |229 bb.0:230 liveins: $x0, $x1231 ; We shouldn't get a SUB here, because "cmp wN, $0" and "cmp wN, #0" have232 ; opposite effects on the C flag.233 ; CHECK-LABEL: name: add_imm_0_s32234 ; CHECK: liveins: $x0, $x1235 ; CHECK-NEXT: {{ $}}236 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0237 ; CHECK-NEXT: [[ADDXri:%[0-9]+]]:gpr64sp = ADDXri [[COPY]], 0, 0238 ; CHECK-NEXT: $x0 = COPY [[ADDXri]]239 %0(s64) = COPY $x0240 %1(s64) = G_CONSTANT i64 0241 %2(s64) = G_ADD %0, %1242 $x0 = COPY %2(s64)243...244 245---246name: add_imm_0_s64247legalized: true248regBankSelected: true249 250registers:251 - { id: 0, class: gpr }252 - { id: 1, class: gpr }253 - { id: 2, class: gpr }254 255body: |256 bb.0:257 liveins: $x0, $x1258 ; We shouldn't get a SUB here, because "cmp xN, $0" and "cmp xN, #0" have259 ; opposite effects on the C flag.260 ; CHECK-LABEL: name: add_imm_0_s64261 ; CHECK: liveins: $x0, $x1262 ; CHECK-NEXT: {{ $}}263 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0264 ; CHECK-NEXT: [[ADDXri:%[0-9]+]]:gpr64sp = ADDXri [[COPY]], 0, 0265 ; CHECK-NEXT: $x0 = COPY [[ADDXri]]266 %0(s64) = COPY $x0267 %1(s64) = G_CONSTANT i64 0268 %2(s64) = G_ADD %0, %1269 $x0 = COPY %2(s64)270...271 272---273name: add_imm_s32_gpr_bb274legalized: true275regBankSelected: true276 277registers:278 - { id: 0, class: gpr }279 - { id: 1, class: gpr }280 - { id: 2, class: gpr }281 282body: |283 ; CHECK-LABEL: name: add_imm_s32_gpr_bb284 ; CHECK: bb.0:285 ; CHECK-NEXT: successors: %bb.1(0x80000000)286 ; CHECK-NEXT: liveins: $w0, $w1287 ; CHECK-NEXT: {{ $}}288 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32sp = COPY $w0289 ; CHECK-NEXT: B %bb.1290 ; CHECK-NEXT: {{ $}}291 ; CHECK-NEXT: bb.1:292 ; CHECK-NEXT: [[ADDWri:%[0-9]+]]:gpr32sp = ADDWri [[COPY]], 1, 0293 ; CHECK-NEXT: $w0 = COPY [[ADDWri]]294 bb.0:295 liveins: $w0, $w1296 successors: %bb.1297 298 %0(s32) = COPY $w0299 %1(s32) = G_CONSTANT i32 1300 G_BR %bb.1301 302 bb.1:303 %2(s32) = G_ADD %0, %1304 $w0 = COPY %2(s32)305...306 307---308# Same as add_s32_gpr, for G_SUB operations.309name: sub_s32_gpr310legalized: true311regBankSelected: true312 313registers:314 - { id: 0, class: gpr }315 - { id: 1, class: gpr }316 - { id: 2, class: gpr }317 318body: |319 bb.0:320 liveins: $w0, $w1321 322 ; CHECK-LABEL: name: sub_s32_gpr323 ; CHECK: liveins: $w0, $w1324 ; CHECK-NEXT: {{ $}}325 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0326 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1327 ; CHECK-NEXT: [[SUBSWrr:%[0-9]+]]:gpr32 = SUBSWrr [[COPY]], [[COPY1]], implicit-def dead $nzcv328 ; CHECK-NEXT: $w0 = COPY [[SUBSWrr]]329 %0(s32) = COPY $w0330 %1(s32) = COPY $w1331 %2(s32) = G_SUB %0, %1332 $w0 = COPY %2(s32)333...334 335---336# Same as add_s64_gpr, for G_SUB operations.337name: sub_s64_gpr338legalized: true339regBankSelected: true340 341registers:342 - { id: 0, class: gpr }343 - { id: 1, class: gpr }344 - { id: 2, class: gpr }345 346body: |347 bb.0:348 liveins: $x0, $x1349 350 ; CHECK-LABEL: name: sub_s64_gpr351 ; CHECK: liveins: $x0, $x1352 ; CHECK-NEXT: {{ $}}353 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0354 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1355 ; CHECK-NEXT: [[SUBSXrr:%[0-9]+]]:gpr64 = SUBSXrr [[COPY]], [[COPY1]], implicit-def dead $nzcv356 ; CHECK-NEXT: $x0 = COPY [[SUBSXrr]]357 %0(s64) = COPY $x0358 %1(s64) = COPY $x1359 %2(s64) = G_SUB %0, %1360 $x0 = COPY %2(s64)361...362 363---364# Same as add_s32_gpr, for G_OR operations.365name: or_s32_gpr366legalized: true367regBankSelected: true368 369registers:370 - { id: 0, class: gpr }371 - { id: 1, class: gpr }372 - { id: 2, class: gpr }373 374body: |375 bb.0:376 liveins: $w0, $w1377 378 ; CHECK-LABEL: name: or_s32_gpr379 ; CHECK: liveins: $w0, $w1380 ; CHECK-NEXT: {{ $}}381 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0382 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1383 ; CHECK-NEXT: [[ORRWrr:%[0-9]+]]:gpr32 = ORRWrr [[COPY]], [[COPY1]]384 ; CHECK-NEXT: $w0 = COPY [[ORRWrr]]385 %0(s32) = COPY $w0386 %1(s32) = COPY $w1387 %2(s32) = G_OR %0, %1388 $w0 = COPY %2(s32)389...390 391---392# Same as add_s64_gpr, for G_OR operations.393name: or_s64_gpr394legalized: true395regBankSelected: true396 397registers:398 - { id: 0, class: gpr }399 - { id: 1, class: gpr }400 - { id: 2, class: gpr }401 402body: |403 bb.0:404 liveins: $x0, $x1405 406 ; CHECK-LABEL: name: or_s64_gpr407 ; CHECK: liveins: $x0, $x1408 ; CHECK-NEXT: {{ $}}409 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0410 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1411 ; CHECK-NEXT: [[ORRXrr:%[0-9]+]]:gpr64 = ORRXrr [[COPY]], [[COPY1]]412 ; CHECK-NEXT: $x0 = COPY [[ORRXrr]]413 %0(s64) = COPY $x0414 %1(s64) = COPY $x1415 %2(s64) = G_OR %0, %1416 $x0 = COPY %2(s64)417...418 419---420# 64-bit G_OR on vector registers.421name: or_v2s32_fpr422legalized: true423regBankSelected: true424#425registers:426 - { id: 0, class: fpr }427 - { id: 1, class: fpr }428 - { id: 2, class: fpr }429 430# The actual OR does not matter as long as it is operating431# on 64-bit width vector.432body: |433 bb.0:434 liveins: $d0, $d1435 436 ; CHECK-LABEL: name: or_v2s32_fpr437 ; CHECK: liveins: $d0, $d1438 ; CHECK-NEXT: {{ $}}439 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0440 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1441 ; CHECK-NEXT: [[ORRv8i8_:%[0-9]+]]:fpr64 = ORRv8i8 [[COPY]], [[COPY1]]442 ; CHECK-NEXT: $d0 = COPY [[ORRv8i8_]]443 %0(<2 x s32>) = COPY $d0444 %1(<2 x s32>) = COPY $d1445 %2(<2 x s32>) = G_OR %0, %1446 $d0 = COPY %2(<2 x s32>)447...448 449---450# Same as add_s32_gpr, for G_AND operations.451name: and_s32_gpr452legalized: true453regBankSelected: true454 455registers:456 - { id: 0, class: gpr }457 - { id: 1, class: gpr }458 - { id: 2, class: gpr }459 460body: |461 bb.0:462 liveins: $w0, $w1463 464 ; CHECK-LABEL: name: and_s32_gpr465 ; CHECK: liveins: $w0, $w1466 ; CHECK-NEXT: {{ $}}467 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0468 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1469 ; CHECK-NEXT: [[ANDWrr:%[0-9]+]]:gpr32 = ANDWrr [[COPY]], [[COPY1]]470 ; CHECK-NEXT: $w0 = COPY [[ANDWrr]]471 %0(s32) = COPY $w0472 %1(s32) = COPY $w1473 %2(s32) = G_AND %0, %1474 $w0 = COPY %2(s32)475...476 477---478# Same as add_s64_gpr, for G_AND operations.479name: and_s64_gpr480legalized: true481regBankSelected: true482 483registers:484 - { id: 0, class: gpr }485 - { id: 1, class: gpr }486 - { id: 2, class: gpr }487 488body: |489 bb.0:490 liveins: $x0, $x1491 492 ; CHECK-LABEL: name: and_s64_gpr493 ; CHECK: liveins: $x0, $x1494 ; CHECK-NEXT: {{ $}}495 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0496 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1497 ; CHECK-NEXT: [[ANDXrr:%[0-9]+]]:gpr64 = ANDXrr [[COPY]], [[COPY1]]498 ; CHECK-NEXT: $x0 = COPY [[ANDXrr]]499 %0(s64) = COPY $x0500 %1(s64) = COPY $x1501 %2(s64) = G_AND %0, %1502 $x0 = COPY %2(s64)503...504 505---506# Same as add_s32_gpr, for G_SHL operations.507name: shl_s32_gpr508legalized: true509regBankSelected: true510 511registers:512 - { id: 0, class: gpr }513 - { id: 1, class: gpr }514 - { id: 2, class: gpr }515 516body: |517 bb.0:518 liveins: $w0, $w1519 520 ; CHECK-LABEL: name: shl_s32_gpr521 ; CHECK: liveins: $w0, $w1522 ; CHECK-NEXT: {{ $}}523 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0524 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1525 ; CHECK-NEXT: [[LSLVWr:%[0-9]+]]:gpr32 = LSLVWr [[COPY]], [[COPY1]]526 ; CHECK-NEXT: $w0 = COPY [[LSLVWr]]527 %0(s32) = COPY $w0528 %1(s32) = COPY $w1529 %2(s32) = G_SHL %0, %1530 $w0 = COPY %2(s32)531...532 533---534name: shl_s32_64_gpr535legalized: true536regBankSelected: true537 538registers:539 - { id: 0, class: gpr }540 - { id: 1, class: gpr }541 - { id: 2, class: gpr }542 543body: |544 bb.0:545 liveins: $w0, $x1546 547 ; CHECK-LABEL: name: shl_s32_64_gpr548 ; CHECK: liveins: $w0, $x1549 ; CHECK-NEXT: {{ $}}550 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0551 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1552 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr32 = COPY [[COPY1]].sub_32553 ; CHECK-NEXT: [[LSLVWr:%[0-9]+]]:gpr32 = LSLVWr [[COPY]], [[COPY2]]554 ; CHECK-NEXT: $w0 = COPY [[LSLVWr]]555 %0(s32) = COPY $w0556 %1(s64) = COPY $x1557 %2(s32) = G_SHL %0, %1558 $w0 = COPY %2(s32)559...560 561---562# Same as add_s64_gpr, for G_SHL operations.563name: shl_s64_gpr564legalized: true565regBankSelected: true566 567registers:568 - { id: 0, class: gpr }569 - { id: 1, class: gpr }570 - { id: 2, class: gpr }571 572body: |573 bb.0:574 liveins: $x0, $x1575 576 ; CHECK-LABEL: name: shl_s64_gpr577 ; CHECK: liveins: $x0, $x1578 ; CHECK-NEXT: {{ $}}579 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0580 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1581 ; CHECK-NEXT: [[LSLVXr:%[0-9]+]]:gpr64 = LSLVXr [[COPY]], [[COPY1]]582 ; CHECK-NEXT: $x0 = COPY [[LSLVXr]]583 %0(s64) = COPY $x0584 %1(s64) = COPY $x1585 %2(s64) = G_SHL %0, %1586 $x0 = COPY %2(s64)587...588 589---590# Same as add_s32_gpr, for G_LSHR operations.591name: lshr_s32_gpr592legalized: true593regBankSelected: true594 595registers:596 - { id: 0, class: gpr }597 - { id: 1, class: gpr }598 - { id: 2, class: gpr }599 600body: |601 bb.0:602 liveins: $w0, $w1603 604 ; CHECK-LABEL: name: lshr_s32_gpr605 ; CHECK: liveins: $w0, $w1606 ; CHECK-NEXT: {{ $}}607 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0608 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1609 ; CHECK-NEXT: [[LSRVWr:%[0-9]+]]:gpr32 = LSRVWr [[COPY]], [[COPY1]]610 ; CHECK-NEXT: $w0 = COPY [[LSRVWr]]611 %0(s32) = COPY $w0612 %1(s32) = COPY $w1613 %2(s32) = G_LSHR %0, %1614 $w0 = COPY %2(s32)615...616 617---618# Same as add_s64_gpr, for G_LSHR operations.619name: lshr_s64_gpr620legalized: true621regBankSelected: true622 623registers:624 - { id: 0, class: gpr }625 - { id: 1, class: gpr }626 - { id: 2, class: gpr }627 628body: |629 bb.0:630 liveins: $x0, $x1631 632 ; CHECK-LABEL: name: lshr_s64_gpr633 ; CHECK: liveins: $x0, $x1634 ; CHECK-NEXT: {{ $}}635 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0636 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1637 ; CHECK-NEXT: [[LSRVXr:%[0-9]+]]:gpr64 = LSRVXr [[COPY]], [[COPY1]]638 ; CHECK-NEXT: $x0 = COPY [[LSRVXr]]639 %0(s64) = COPY $x0640 %1(s64) = COPY $x1641 %2(s64) = G_LSHR %0, %1642 $x0 = COPY %2(s64)643...644 645---646# Same as add_s32_gpr, for G_ASHR operations.647name: ashr_s32_gpr648legalized: true649regBankSelected: true650 651registers:652 - { id: 0, class: gpr }653 - { id: 1, class: gpr }654 - { id: 2, class: gpr }655 656body: |657 bb.0:658 liveins: $w0, $w1659 660 ; CHECK-LABEL: name: ashr_s32_gpr661 ; CHECK: liveins: $w0, $w1662 ; CHECK-NEXT: {{ $}}663 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0664 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1665 ; CHECK-NEXT: [[ASRVWr:%[0-9]+]]:gpr32 = ASRVWr [[COPY]], [[COPY1]]666 ; CHECK-NEXT: $w0 = COPY [[ASRVWr]]667 %0(s32) = COPY $w0668 %1(s32) = COPY $w1669 %2(s32) = G_ASHR %0, %1670 $w0 = COPY %2(s32)671...672 673---674# Same as add_s64_gpr, for G_ASHR operations.675name: ashr_s64_gpr676legalized: true677regBankSelected: true678 679registers:680 - { id: 0, class: gpr }681 - { id: 1, class: gpr }682 - { id: 2, class: gpr }683 684body: |685 bb.0:686 liveins: $x0, $x1687 688 ; CHECK-LABEL: name: ashr_s64_gpr689 ; CHECK: liveins: $x0, $x1690 ; CHECK-NEXT: {{ $}}691 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0692 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1693 ; CHECK-NEXT: [[ASRVXr:%[0-9]+]]:gpr64 = ASRVXr [[COPY]], [[COPY1]]694 ; CHECK-NEXT: $x0 = COPY [[ASRVXr]]695 %0(s64) = COPY $x0696 %1(s64) = COPY $x1697 %2(s64) = G_ASHR %0, %1698 $x0 = COPY %2(s64)699...700 701---702# Check that we select s32 GPR G_MUL. This is trickier than other binops because703# there is only MADDWrrr, and we have to use the WZR physreg.704name: mul_s32_gpr705legalized: true706regBankSelected: true707 708registers:709 - { id: 0, class: gpr }710 - { id: 1, class: gpr }711 - { id: 2, class: gpr }712 713body: |714 bb.0:715 liveins: $w0, $w1716 717 ; CHECK-LABEL: name: mul_s32_gpr718 ; CHECK: liveins: $w0, $w1719 ; CHECK-NEXT: {{ $}}720 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0721 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1722 ; CHECK-NEXT: [[MADDWrrr:%[0-9]+]]:gpr32 = MADDWrrr [[COPY]], [[COPY1]], $wzr723 ; CHECK-NEXT: $w0 = COPY [[MADDWrrr]]724 %0(s32) = COPY $w0725 %1(s32) = COPY $w1726 %2(s32) = G_MUL %0, %1727 $w0 = COPY %2(s32)728...729 730---731# Same as mul_s32_gpr for the s64 type.732name: mul_s64_gpr733legalized: true734regBankSelected: true735 736registers:737 - { id: 0, class: gpr }738 - { id: 1, class: gpr }739 - { id: 2, class: gpr }740 741body: |742 bb.0:743 liveins: $x0, $x1744 745 ; CHECK-LABEL: name: mul_s64_gpr746 ; CHECK: liveins: $x0, $x1747 ; CHECK-NEXT: {{ $}}748 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0749 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1750 ; CHECK-NEXT: [[MADDXrrr:%[0-9]+]]:gpr64 = MADDXrrr [[COPY]], [[COPY1]], $xzr751 ; CHECK-NEXT: $x0 = COPY [[MADDXrrr]]752 %0(s64) = COPY $x0753 %1(s64) = COPY $x1754 %2(s64) = G_MUL %0, %1755 $x0 = COPY %2(s64)756...757 758---759# Same as mul_s32_gpr for the s64 type.760name: mulh_s64_gpr761legalized: true762regBankSelected: true763 764 765body: |766 bb.0:767 liveins: $x0, $x1768 769 ; CHECK-LABEL: name: mulh_s64_gpr770 ; CHECK: liveins: $x0, $x1771 ; CHECK-NEXT: {{ $}}772 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0773 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1774 ; CHECK-NEXT: [[SMULHrr:%[0-9]+]]:gpr64 = SMULHrr [[COPY]], [[COPY1]]775 ; CHECK-NEXT: [[UMULHrr:%[0-9]+]]:gpr64 = UMULHrr [[COPY]], [[COPY1]]776 ; CHECK-NEXT: $x0 = COPY [[SMULHrr]]777 ; CHECK-NEXT: $x0 = COPY [[UMULHrr]]778 %0:gpr(s64) = COPY $x0779 %1:gpr(s64) = COPY $x1780 %2:gpr(s64) = G_SMULH %0, %1781 %3:gpr(s64) = G_UMULH %0, %1782 $x0 = COPY %2(s64)783 $x0 = COPY %3(s64)784...785 786---787# Same as add_s32_gpr, for G_SDIV operations.788name: sdiv_s32_gpr789legalized: true790regBankSelected: true791 792registers:793 - { id: 0, class: gpr }794 - { id: 1, class: gpr }795 - { id: 2, class: gpr }796 797body: |798 bb.0:799 liveins: $w0, $w1800 801 ; CHECK-LABEL: name: sdiv_s32_gpr802 ; CHECK: liveins: $w0, $w1803 ; CHECK-NEXT: {{ $}}804 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0805 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1806 ; CHECK-NEXT: [[SDIVWr:%[0-9]+]]:gpr32 = SDIVWr [[COPY]], [[COPY1]]807 ; CHECK-NEXT: $w0 = COPY [[SDIVWr]]808 %0(s32) = COPY $w0809 %1(s32) = COPY $w1810 %2(s32) = G_SDIV %0, %1811 $w0 = COPY %2(s32)812...813 814---815# Same as add_s64_gpr, for G_SDIV operations.816name: sdiv_s64_gpr817legalized: true818regBankSelected: true819 820registers:821 - { id: 0, class: gpr }822 - { id: 1, class: gpr }823 - { id: 2, class: gpr }824 825body: |826 bb.0:827 liveins: $x0, $x1828 829 ; CHECK-LABEL: name: sdiv_s64_gpr830 ; CHECK: liveins: $x0, $x1831 ; CHECK-NEXT: {{ $}}832 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0833 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1834 ; CHECK-NEXT: [[SDIVXr:%[0-9]+]]:gpr64 = SDIVXr [[COPY]], [[COPY1]]835 ; CHECK-NEXT: $x0 = COPY [[SDIVXr]]836 %0(s64) = COPY $x0837 %1(s64) = COPY $x1838 %2(s64) = G_SDIV %0, %1839 $x0 = COPY %2(s64)840...841 842---843# Same as add_s32_gpr, for G_UDIV operations.844name: udiv_s32_gpr845legalized: true846regBankSelected: true847 848registers:849 - { id: 0, class: gpr }850 - { id: 1, class: gpr }851 - { id: 2, class: gpr }852 853body: |854 bb.0:855 liveins: $w0, $w1856 857 ; CHECK-LABEL: name: udiv_s32_gpr858 ; CHECK: liveins: $w0, $w1859 ; CHECK-NEXT: {{ $}}860 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0861 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1862 ; CHECK-NEXT: [[UDIVWr:%[0-9]+]]:gpr32 = UDIVWr [[COPY]], [[COPY1]]863 ; CHECK-NEXT: $w0 = COPY [[UDIVWr]]864 %0(s32) = COPY $w0865 %1(s32) = COPY $w1866 %2(s32) = G_UDIV %0, %1867 $w0 = COPY %2(s32)868...869 870---871# Same as add_s64_gpr, for G_UDIV operations.872name: udiv_s64_gpr873legalized: true874regBankSelected: true875 876registers:877 - { id: 0, class: gpr }878 - { id: 1, class: gpr }879 - { id: 2, class: gpr }880 881body: |882 bb.0:883 liveins: $x0, $x1884 885 ; CHECK-LABEL: name: udiv_s64_gpr886 ; CHECK: liveins: $x0, $x1887 ; CHECK-NEXT: {{ $}}888 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0889 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1890 ; CHECK-NEXT: [[UDIVXr:%[0-9]+]]:gpr64 = UDIVXr [[COPY]], [[COPY1]]891 ; CHECK-NEXT: $x0 = COPY [[UDIVXr]]892 %0(s64) = COPY $x0893 %1(s64) = COPY $x1894 %2(s64) = G_UDIV %0, %1895 $x0 = COPY %2(s64)896...897 898---899# Check that we select a s32 FPR G_FADD into FADDSrr.900name: fadd_s32_fpr901legalized: true902regBankSelected: true903 904registers:905 - { id: 0, class: fpr }906 - { id: 1, class: fpr }907 - { id: 2, class: fpr }908 909body: |910 bb.0:911 liveins: $s0, $s1912 913 ; CHECK-LABEL: name: fadd_s32_fpr914 ; CHECK: liveins: $s0, $s1915 ; CHECK-NEXT: {{ $}}916 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $s0917 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr32 = COPY $s1918 ; CHECK-NEXT: [[FADDSrr:%[0-9]+]]:fpr32 = nofpexcept FADDSrr [[COPY]], [[COPY1]], implicit $fpcr919 ; CHECK-NEXT: $s0 = COPY [[FADDSrr]]920 %0(s32) = COPY $s0921 %1(s32) = COPY $s1922 %2(s32) = G_FADD %0, %1923 $s0 = COPY %2(s32)924...925 926---927name: fadd_s64_fpr928legalized: true929regBankSelected: true930 931registers:932 - { id: 0, class: fpr }933 - { id: 1, class: fpr }934 - { id: 2, class: fpr }935 936body: |937 bb.0:938 liveins: $d0, $d1939 940 ; CHECK-LABEL: name: fadd_s64_fpr941 ; CHECK: liveins: $d0, $d1942 ; CHECK-NEXT: {{ $}}943 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0944 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1945 ; CHECK-NEXT: [[FADDDrr:%[0-9]+]]:fpr64 = nofpexcept FADDDrr [[COPY]], [[COPY1]], implicit $fpcr946 ; CHECK-NEXT: $d0 = COPY [[FADDDrr]]947 %0(s64) = COPY $d0948 %1(s64) = COPY $d1949 %2(s64) = G_FADD %0, %1950 $d0 = COPY %2(s64)951...952 953---954name: fsub_s32_fpr955legalized: true956regBankSelected: true957 958registers:959 - { id: 0, class: fpr }960 - { id: 1, class: fpr }961 - { id: 2, class: fpr }962 963body: |964 bb.0:965 liveins: $s0, $s1966 967 ; CHECK-LABEL: name: fsub_s32_fpr968 ; CHECK: liveins: $s0, $s1969 ; CHECK-NEXT: {{ $}}970 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $s0971 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr32 = COPY $s1972 ; CHECK-NEXT: [[FSUBSrr:%[0-9]+]]:fpr32 = nofpexcept FSUBSrr [[COPY]], [[COPY1]], implicit $fpcr973 ; CHECK-NEXT: $s0 = COPY [[FSUBSrr]]974 %0(s32) = COPY $s0975 %1(s32) = COPY $s1976 %2(s32) = G_FSUB %0, %1977 $s0 = COPY %2(s32)978...979 980---981name: fsub_s64_fpr982legalized: true983regBankSelected: true984 985registers:986 - { id: 0, class: fpr }987 - { id: 1, class: fpr }988 - { id: 2, class: fpr }989 990body: |991 bb.0:992 liveins: $d0, $d1993 994 ; CHECK-LABEL: name: fsub_s64_fpr995 ; CHECK: liveins: $d0, $d1996 ; CHECK-NEXT: {{ $}}997 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0998 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1999 ; CHECK-NEXT: [[FSUBDrr:%[0-9]+]]:fpr64 = nofpexcept FSUBDrr [[COPY]], [[COPY1]], implicit $fpcr1000 ; CHECK-NEXT: $d0 = COPY [[FSUBDrr]]1001 %0(s64) = COPY $d01002 %1(s64) = COPY $d11003 %2(s64) = G_FSUB %0, %11004 $d0 = COPY %2(s64)1005...1006 1007---1008name: fmul_s32_fpr1009legalized: true1010regBankSelected: true1011 1012registers:1013 - { id: 0, class: fpr }1014 - { id: 1, class: fpr }1015 - { id: 2, class: fpr }1016 1017body: |1018 bb.0:1019 liveins: $s0, $s11020 1021 ; CHECK-LABEL: name: fmul_s32_fpr1022 ; CHECK: liveins: $s0, $s11023 ; CHECK-NEXT: {{ $}}1024 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $s01025 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr32 = COPY $s11026 ; CHECK-NEXT: [[FMULSrr:%[0-9]+]]:fpr32 = nofpexcept FMULSrr [[COPY]], [[COPY1]], implicit $fpcr1027 ; CHECK-NEXT: $s0 = COPY [[FMULSrr]]1028 %0(s32) = COPY $s01029 %1(s32) = COPY $s11030 %2(s32) = G_FMUL %0, %11031 $s0 = COPY %2(s32)1032...1033 1034---1035name: fmul_s64_fpr1036legalized: true1037regBankSelected: true1038 1039registers:1040 - { id: 0, class: fpr }1041 - { id: 1, class: fpr }1042 - { id: 2, class: fpr }1043 1044body: |1045 bb.0:1046 liveins: $d0, $d11047 1048 ; CHECK-LABEL: name: fmul_s64_fpr1049 ; CHECK: liveins: $d0, $d11050 ; CHECK-NEXT: {{ $}}1051 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d01052 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d11053 ; CHECK-NEXT: [[FMULDrr:%[0-9]+]]:fpr64 = nofpexcept FMULDrr [[COPY]], [[COPY1]], implicit $fpcr1054 ; CHECK-NEXT: $d0 = COPY [[FMULDrr]]1055 %0(s64) = COPY $d01056 %1(s64) = COPY $d11057 %2(s64) = G_FMUL %0, %11058 $d0 = COPY %2(s64)1059...1060 1061---1062name: fdiv_s32_fpr1063legalized: true1064regBankSelected: true1065 1066registers:1067 - { id: 0, class: fpr }1068 - { id: 1, class: fpr }1069 - { id: 2, class: fpr }1070 1071body: |1072 bb.0:1073 liveins: $s0, $s11074 1075 ; CHECK-LABEL: name: fdiv_s32_fpr1076 ; CHECK: liveins: $s0, $s11077 ; CHECK-NEXT: {{ $}}1078 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $s01079 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr32 = COPY $s11080 ; CHECK-NEXT: [[FDIVSrr:%[0-9]+]]:fpr32 = nofpexcept FDIVSrr [[COPY]], [[COPY1]], implicit $fpcr1081 ; CHECK-NEXT: $s0 = COPY [[FDIVSrr]]1082 %0(s32) = COPY $s01083 %1(s32) = COPY $s11084 %2(s32) = G_FDIV %0, %11085 $s0 = COPY %2(s32)1086...1087 1088---1089name: fdiv_s64_fpr1090legalized: true1091regBankSelected: true1092 1093registers:1094 - { id: 0, class: fpr }1095 - { id: 1, class: fpr }1096 - { id: 2, class: fpr }1097 1098body: |1099 bb.0:1100 liveins: $d0, $d11101 1102 ; CHECK-LABEL: name: fdiv_s64_fpr1103 ; CHECK: liveins: $d0, $d11104 ; CHECK-NEXT: {{ $}}1105 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d01106 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d11107 ; CHECK-NEXT: [[FDIVDrr:%[0-9]+]]:fpr64 = nofpexcept FDIVDrr [[COPY]], [[COPY1]], implicit $fpcr1108 ; CHECK-NEXT: $d0 = COPY [[FDIVDrr]]1109 %0(s64) = COPY $d01110 %1(s64) = COPY $d11111 %2(s64) = G_FDIV %0, %11112 $d0 = COPY %2(s64)1113...1114---1115name: add_v8i161116alignment: 41117legalized: true1118regBankSelected: true1119tracksRegLiveness: true1120registers:1121 - { id: 0, class: fpr }1122 - { id: 1, class: fpr }1123 - { id: 2, class: fpr }1124machineFunctionInfo: {}1125body: |1126 bb.1:1127 liveins: $q0, $q11128 1129 ; CHECK-LABEL: name: add_v8i161130 ; CHECK: liveins: $q0, $q11131 ; CHECK-NEXT: {{ $}}1132 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q01133 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q11134 ; CHECK-NEXT: [[ADDv8i16_:%[0-9]+]]:fpr128 = ADDv8i16 [[COPY]], [[COPY1]]1135 ; CHECK-NEXT: $q0 = COPY [[ADDv8i16_]]1136 ; CHECK-NEXT: RET_ReallyLR implicit $q01137 %0:fpr(<8 x s16>) = COPY $q01138 %1:fpr(<8 x s16>) = COPY $q11139 %2:fpr(<8 x s16>) = G_ADD %0, %11140 $q0 = COPY %2(<8 x s16>)1141 RET_ReallyLR implicit $q01142 1143...1144---1145name: add_v16i81146alignment: 41147legalized: true1148regBankSelected: true1149tracksRegLiveness: true1150registers:1151 - { id: 0, class: fpr }1152 - { id: 1, class: fpr }1153 - { id: 2, class: fpr }1154machineFunctionInfo: {}1155body: |1156 bb.1:1157 liveins: $q0, $q11158 1159 ; CHECK-LABEL: name: add_v16i81160 ; CHECK: liveins: $q0, $q11161 ; CHECK-NEXT: {{ $}}1162 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q01163 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q11164 ; CHECK-NEXT: [[ADDv16i8_:%[0-9]+]]:fpr128 = ADDv16i8 [[COPY]], [[COPY1]]1165 ; CHECK-NEXT: $q0 = COPY [[ADDv16i8_]]1166 ; CHECK-NEXT: RET_ReallyLR implicit $q01167 %0:fpr(<16 x s8>) = COPY $q01168 %1:fpr(<16 x s8>) = COPY $q11169 %2:fpr(<16 x s8>) = G_ADD %0, %11170 $q0 = COPY %2(<16 x s8>)1171 RET_ReallyLR implicit $q01172 1173...1174---1175name: add_v4i161176legalized: true1177regBankSelected: true1178tracksRegLiveness: true1179body: |1180 bb.1:1181 liveins: $d0, $d11182 1183 ; CHECK-LABEL: name: add_v4i161184 ; CHECK: liveins: $d0, $d11185 ; CHECK-NEXT: {{ $}}1186 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d01187 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d11188 ; CHECK-NEXT: [[ADDv4i16_:%[0-9]+]]:fpr64 = ADDv4i16 [[COPY]], [[COPY1]]1189 ; CHECK-NEXT: $d0 = COPY [[ADDv4i16_]]1190 ; CHECK-NEXT: RET_ReallyLR implicit $d01191 %0:fpr(<4 x s16>) = COPY $d01192 %1:fpr(<4 x s16>) = COPY $d11193 %2:fpr(<4 x s16>) = G_ADD %0, %11194 $d0 = COPY %2(<4 x s16>)1195 RET_ReallyLR implicit $d01196...1197---1198name: or_v4i161199legalized: true1200regBankSelected: true1201tracksRegLiveness: true1202body: |1203 bb.1:1204 liveins: $d0, $d11205 1206 ; CHECK-LABEL: name: or_v4i161207 ; CHECK: liveins: $d0, $d11208 ; CHECK-NEXT: {{ $}}1209 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d01210 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d11211 ; CHECK-NEXT: [[ORRv8i8_:%[0-9]+]]:fpr64 = ORRv8i8 [[COPY]], [[COPY1]]1212 ; CHECK-NEXT: $d0 = COPY [[ORRv8i8_]]1213 ; CHECK-NEXT: RET_ReallyLR implicit $d01214 %0:fpr(<4 x s16>) = COPY $d01215 %1:fpr(<4 x s16>) = COPY $d11216 %2:fpr(<4 x s16>) = G_OR %0, %11217 $d0 = COPY %2(<4 x s16>)1218 RET_ReallyLR implicit $d01219...1220---1221name: xor_v4i161222legalized: true1223regBankSelected: true1224tracksRegLiveness: true1225body: |1226 bb.1:1227 liveins: $d0, $d11228 1229 ; CHECK-LABEL: name: xor_v4i161230 ; CHECK: liveins: $d0, $d11231 ; CHECK-NEXT: {{ $}}1232 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d01233 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d11234 ; CHECK-NEXT: [[EORv8i8_:%[0-9]+]]:fpr64 = EORv8i8 [[COPY]], [[COPY1]]1235 ; CHECK-NEXT: $d0 = COPY [[EORv8i8_]]1236 ; CHECK-NEXT: RET_ReallyLR implicit $d01237 %0:fpr(<4 x s16>) = COPY $d01238 %1:fpr(<4 x s16>) = COPY $d11239 %2:fpr(<4 x s16>) = G_XOR %0, %11240 $d0 = COPY %2(<4 x s16>)1241 RET_ReallyLR implicit $d01242...1243---1244name: mul_v4i161245legalized: true1246regBankSelected: true1247tracksRegLiveness: true1248body: |1249 bb.1:1250 liveins: $d0, $d11251 1252 ; CHECK-LABEL: name: mul_v4i161253 ; CHECK: liveins: $d0, $d11254 ; CHECK-NEXT: {{ $}}1255 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d01256 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d11257 ; CHECK-NEXT: [[MULv4i16_:%[0-9]+]]:fpr64 = MULv4i16 [[COPY]], [[COPY1]]1258 ; CHECK-NEXT: $d0 = COPY [[MULv4i16_]]1259 ; CHECK-NEXT: RET_ReallyLR implicit $d01260 %0:fpr(<4 x s16>) = COPY $d01261 %1:fpr(<4 x s16>) = COPY $d11262 %2:fpr(<4 x s16>) = G_MUL %0, %11263 $d0 = COPY %2(<4 x s16>)1264 RET_ReallyLR implicit $d01265...1266