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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple aarch64 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s3 4...5---6name: s327legalized: true8regBankSelected: true9tracksRegLiveness: true10body: |11 bb.0:12 liveins: $w013 14 ; CHECK-LABEL: name: s3215 ; CHECK: liveins: $w016 ; CHECK-NEXT: {{ $}}17 ; CHECK-NEXT: %copy:gpr32 = COPY $w018 ; CHECK-NEXT: %bitreverse:gpr32 = RBITWr %copy19 ; CHECK-NEXT: $w0 = COPY %bitreverse20 ; CHECK-NEXT: RET_ReallyLR implicit $w021 %copy:gpr(s32) = COPY $w022 %bitreverse:gpr(s32) = G_BITREVERSE %copy23 $w0 = COPY %bitreverse(s32)24 RET_ReallyLR implicit $w025 26...27---28name: s6429legalized: true30regBankSelected: true31tracksRegLiveness: true32body: |33 bb.0:34 liveins: $x035 36 ; CHECK-LABEL: name: s6437 ; CHECK: liveins: $x038 ; CHECK-NEXT: {{ $}}39 ; CHECK-NEXT: %copy:gpr64 = COPY $x040 ; CHECK-NEXT: %bitreverse:gpr64 = RBITXr %copy41 ; CHECK-NEXT: $x0 = COPY %bitreverse42 ; CHECK-NEXT: RET_ReallyLR implicit $x043 %copy:gpr(s64) = COPY $x044 %bitreverse:gpr(s64) = G_BITREVERSE %copy45 $x0 = COPY %bitreverse(s64)46 RET_ReallyLR implicit $x047 48...49---50name: v8s8_legal51legalized: true52regBankSelected: true53tracksRegLiveness: true54body: |55 bb.0:56 liveins: $x057 58 ; CHECK-LABEL: name: v8s8_legal59 ; CHECK: liveins: $x060 ; CHECK-NEXT: {{ $}}61 ; CHECK-NEXT: %vec:fpr64 = IMPLICIT_DEF62 ; CHECK-NEXT: %bitreverse:fpr64 = RBITv8i8 %vec63 ; CHECK-NEXT: $x0 = COPY %bitreverse64 ; CHECK-NEXT: RET_ReallyLR implicit $x065 %vec:fpr(<8 x s8>) = G_IMPLICIT_DEF66 %bitreverse:fpr(<8 x s8>) = G_BITREVERSE %vec67 $x0 = COPY %bitreverse(<8 x s8>)68 RET_ReallyLR implicit $x069 70...71---72name: v16s8_legal73legalized: true74regBankSelected: true75tracksRegLiveness: true76body: |77 bb.0:78 liveins: $q079 80 ; CHECK-LABEL: name: v16s8_legal81 ; CHECK: liveins: $q082 ; CHECK-NEXT: {{ $}}83 ; CHECK-NEXT: %vec:fpr128 = IMPLICIT_DEF84 ; CHECK-NEXT: %bitreverse:fpr128 = RBITv16i8 %vec85 ; CHECK-NEXT: $q0 = COPY %bitreverse86 ; CHECK-NEXT: RET_ReallyLR implicit $q087 %vec:fpr(<16 x s8>) = G_IMPLICIT_DEF88 %bitreverse:fpr(<16 x s8>) = G_BITREVERSE %vec89 $q0 = COPY %bitreverse(<16 x s8>)90 RET_ReallyLR implicit $q091 92...93