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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s3---4name: condbr_of_not5legalized: true6regBankSelected: true7liveins:8 - { reg: '$x0' }9body: |10 ; CHECK-LABEL: name: condbr_of_not11 ; CHECK: bb.0:12 ; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)13 ; CHECK-NEXT: liveins: $x014 ; CHECK-NEXT: {{ $}}15 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x016 ; CHECK-NEXT: [[LDRBBui:%[0-9]+]]:gpr32 = LDRBBui [[COPY]], 0 :: (load (s8))17 ; CHECK-NEXT: TBZW [[LDRBBui]], 0, %bb.218 ; CHECK-NEXT: {{ $}}19 ; CHECK-NEXT: bb.1:20 ; CHECK-NEXT: RET_ReallyLR21 ; CHECK-NEXT: {{ $}}22 ; CHECK-NEXT: bb.2:23 ; CHECK-NEXT: RET_ReallyLR24 bb.1:25 successors: %bb.2, %bb.326 liveins: $x027 28 %0:gpr(p0) = COPY $x029 %8:gpr(s8) = G_LOAD %0(p0) :: (load (s8))30 %4:gpr(s32) = G_ANYEXT %8(s8)31 %5:gpr(s32) = G_CONSTANT i32 132 %6:gpr(s32) = G_XOR %4, %533 G_BRCOND %6, %bb.334 35 bb.2:36 RET_ReallyLR37 38 bb.3:39 RET_ReallyLR40 41...42---43name: condbr_of_not_6444legalized: true45regBankSelected: true46liveins:47 - { reg: '$x0' }48body: |49 ; CHECK-LABEL: name: condbr_of_not_6450 ; CHECK: bb.0:51 ; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)52 ; CHECK-NEXT: liveins: $x053 ; CHECK-NEXT: {{ $}}54 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x055 ; CHECK-NEXT: [[LDRBBui:%[0-9]+]]:gpr32 = LDRBBui [[COPY]], 0 :: (load (s8))56 ; CHECK-NEXT: TBZW [[LDRBBui]], 0, %bb.257 ; CHECK-NEXT: {{ $}}58 ; CHECK-NEXT: bb.1:59 ; CHECK-NEXT: RET_ReallyLR60 ; CHECK-NEXT: {{ $}}61 ; CHECK-NEXT: bb.2:62 ; CHECK-NEXT: RET_ReallyLR63 ; TB(N)ZX has no encoding if the bit being tested is < 32, so we should get64 ; TBZW here.65 bb.1:66 successors: %bb.2, %bb.367 liveins: $x068 69 %0:gpr(p0) = COPY $x070 %8:gpr(s8) = G_LOAD %0(p0) :: (load (s8))71 %4:gpr(s64) = G_ANYEXT %8(s8)72 %5:gpr(s64) = G_CONSTANT i64 173 %6:gpr(s64) = G_XOR %4, %574 %3:gpr(s32) = G_TRUNC %6(s64)75 G_BRCOND %3(s32), %bb.376 77 bb.2:78 RET_ReallyLR79 80 bb.3:81 RET_ReallyLR82 83...84---85name: condbr_of_and86legalized: true87regBankSelected: true88body: |89 ; CHECK-LABEL: name: condbr_of_and90 ; CHECK: bb.0:91 ; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)92 ; CHECK-NEXT: liveins: $w093 ; CHECK-NEXT: {{ $}}94 ; CHECK-NEXT: %lhs:gpr32 = COPY $w095 ; CHECK-NEXT: TBNZW %lhs, 0, %bb.296 ; CHECK-NEXT: {{ $}}97 ; CHECK-NEXT: bb.1:98 ; CHECK-NEXT: RET_ReallyLR99 ; CHECK-NEXT: {{ $}}100 ; CHECK-NEXT: bb.2:101 ; CHECK-NEXT: RET_ReallyLR102 bb.1:103 successors: %bb.2, %bb.3104 liveins: $w0105 %lhs:gpr(s32) = COPY $w0106 %rhs:gpr(s32) = G_CONSTANT i32 1107 %op:gpr(s32) = G_AND %lhs, %rhs108 G_BRCOND %op, %bb.3109 110 bb.2:111 RET_ReallyLR112 113 bb.3:114 RET_ReallyLR115 116...117---118name: condbr_of_and_no_cst119legalized: true120regBankSelected: true121body: |122 ; CHECK-LABEL: name: condbr_of_and_no_cst123 ; CHECK: bb.0:124 ; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)125 ; CHECK-NEXT: liveins: $w0, $w1126 ; CHECK-NEXT: {{ $}}127 ; CHECK-NEXT: %lhs:gpr32 = COPY $w0128 ; CHECK-NEXT: %rhs:gpr32 = COPY $w1129 ; CHECK-NEXT: %op:gpr32 = ANDWrr %lhs, %rhs130 ; CHECK-NEXT: TBNZW %op, 0, %bb.2131 ; CHECK-NEXT: {{ $}}132 ; CHECK-NEXT: bb.1:133 ; CHECK-NEXT: RET_ReallyLR134 ; CHECK-NEXT: {{ $}}135 ; CHECK-NEXT: bb.2:136 ; CHECK-NEXT: RET_ReallyLR137 bb.1:138 successors: %bb.2, %bb.3139 liveins: $w0, $w1140 %lhs:gpr(s32) = COPY $w0141 %rhs:gpr(s32) = COPY $w1142 %op:gpr(s32) = G_AND %lhs, %rhs143 G_BRCOND %op, %bb.3144 145 bb.2:146 RET_ReallyLR147 148 bb.3:149 RET_ReallyLR150 151...152---153name: condbr_of_shl154legalized: true155regBankSelected: true156body: |157 ; CHECK-LABEL: name: condbr_of_shl158 ; CHECK: bb.0:159 ; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)160 ; CHECK-NEXT: liveins: $w0161 ; CHECK-NEXT: {{ $}}162 ; CHECK-NEXT: %lhs:gpr32 = COPY $w0163 ; CHECK-NEXT: %op:gpr32 = UBFMWri %lhs, 31, 30164 ; CHECK-NEXT: TBNZW %op, 0, %bb.2165 ; CHECK-NEXT: {{ $}}166 ; CHECK-NEXT: bb.1:167 ; CHECK-NEXT: RET_ReallyLR168 ; CHECK-NEXT: {{ $}}169 ; CHECK-NEXT: bb.2:170 ; CHECK-NEXT: RET_ReallyLR171 ; We won't ever fold this, because172 ; bit = 0173 ; bit - constant < 0, which isn't valid for tbz/tbnz.174 bb.1:175 successors: %bb.2, %bb.3176 liveins: $w0177 %lhs:gpr(s32) = COPY $w0178 %rhs:gpr(s32) = G_CONSTANT i32 1179 %op:gpr(s32) = G_SHL %lhs, %rhs180 G_BRCOND %op, %bb.3181 182 bb.2:183 RET_ReallyLR184 185 bb.3:186 RET_ReallyLR187 188...189---190name: condbr_of_ashr191legalized: true192regBankSelected: true193body: |194 ; CHECK-LABEL: name: condbr_of_ashr195 ; CHECK: bb.0:196 ; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)197 ; CHECK-NEXT: liveins: $w0198 ; CHECK-NEXT: {{ $}}199 ; CHECK-NEXT: %lhs:gpr32 = COPY $w0200 ; CHECK-NEXT: TBNZW %lhs, 1, %bb.2201 ; CHECK-NEXT: {{ $}}202 ; CHECK-NEXT: bb.1:203 ; CHECK-NEXT: RET_ReallyLR204 ; CHECK-NEXT: {{ $}}205 ; CHECK-NEXT: bb.2:206 ; CHECK-NEXT: RET_ReallyLR207 ; We can fold ashr, because we can have208 ; (tbz (ashr x, c), 0) where 0 + c > # bits in x.209 bb.1:210 successors: %bb.2, %bb.3211 liveins: $w0212 %lhs:gpr(s32) = COPY $w0213 %rhs:gpr(s32) = G_CONSTANT i32 1214 %op:gpr(s32) = G_ASHR %lhs, %rhs215 G_BRCOND %op, %bb.3216 217 bb.2:218 RET_ReallyLR219 220 bb.3:221 RET_ReallyLR222 223...224---225name: tbnzx226legalized: true227regBankSelected: true228body: |229 ; CHECK-LABEL: name: tbnzx230 ; CHECK: bb.0:231 ; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)232 ; CHECK-NEXT: liveins: $x0233 ; CHECK-NEXT: {{ $}}234 ; CHECK-NEXT: %lhs:gpr64 = COPY $x0235 ; CHECK-NEXT: TBNZX %lhs, 63, %bb.2236 ; CHECK-NEXT: {{ $}}237 ; CHECK-NEXT: bb.1:238 ; CHECK-NEXT: RET_ReallyLR239 ; CHECK-NEXT: {{ $}}240 ; CHECK-NEXT: bb.2:241 ; CHECK-NEXT: RET_ReallyLR242 bb.1:243 successors: %bb.2, %bb.3244 liveins: $x0245 %lhs:gpr(s64) = COPY $x0246 %rhs:gpr(s64) = G_CONSTANT i64 8589934592247 %op:gpr(s64) = G_ASHR %lhs, %rhs248 %trunc:gpr(s32) = G_TRUNC %op(s64)249 G_BRCOND %trunc, %bb.3250 bb.2:251 RET_ReallyLR252 bb.3:253 RET_ReallyLR254...255