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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s3 4...5---6name: bswap_s327legalized: true8regBankSelected: true9 10registers:11 - { id: 0, class: gpr }12 - { id: 1, class: gpr }13 14body: |15 bb.0:16 liveins: $w017 18 ; CHECK-LABEL: name: bswap_s3219 ; CHECK: liveins: $w020 ; CHECK-NEXT: {{ $}}21 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w022 ; CHECK-NEXT: [[REVWr:%[0-9]+]]:gpr32 = REVWr [[COPY]]23 ; CHECK-NEXT: $w0 = COPY [[REVWr]]24 %0(s32) = COPY $w025 %1(s32) = G_BSWAP %026 $w0 = COPY %127...28 29---30name: bswap_s6431legalized: true32regBankSelected: true33 34registers:35 - { id: 0, class: gpr }36 - { id: 1, class: gpr }37 38body: |39 bb.0:40 liveins: $x041 42 ; CHECK-LABEL: name: bswap_s6443 ; CHECK: liveins: $x044 ; CHECK-NEXT: {{ $}}45 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x046 ; CHECK-NEXT: [[REVXr:%[0-9]+]]:gpr64 = REVXr [[COPY]]47 ; CHECK-NEXT: $x0 = COPY [[REVXr]]48 %0(s64) = COPY $x049 %1(s64) = G_BSWAP %050 $x0 = COPY %151 52...53---54name: bswap_v4s1655alignment: 456legalized: true57regBankSelected: true58tracksRegLiveness: true59machineFunctionInfo: {}60body: |61 bb.0:62 liveins: $d063 64 ; CHECK-LABEL: name: bswap_v4s1665 ; CHECK: liveins: $d066 ; CHECK-NEXT: {{ $}}67 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d068 ; CHECK-NEXT: [[REV16v8i8_:%[0-9]+]]:fpr64 = REV16v8i8 [[COPY]]69 ; CHECK-NEXT: $d0 = COPY [[REV16v8i8_]]70 ; CHECK-NEXT: RET_ReallyLR implicit $d071 %0:fpr(<4 x s16>) = COPY $d072 %1:fpr(<4 x s16>) = G_BSWAP %073 $d0 = COPY %1(<4 x s16>)74 RET_ReallyLR implicit $d075 76...77---78name: bswap_v8s1679alignment: 480legalized: true81regBankSelected: true82tracksRegLiveness: true83machineFunctionInfo: {}84body: |85 bb.0:86 liveins: $q087 ; CHECK-LABEL: name: bswap_v8s1688 ; CHECK: liveins: $q089 ; CHECK-NEXT: {{ $}}90 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q091 ; CHECK-NEXT: [[REV16v16i8_:%[0-9]+]]:fpr128 = REV16v16i8 [[COPY]]92 ; CHECK-NEXT: $q0 = COPY [[REV16v16i8_]]93 ; CHECK-NEXT: RET_ReallyLR implicit $q094 %0:fpr(<8 x s16>) = COPY $q095 %1:fpr(<8 x s16>) = G_BSWAP %096 $q0 = COPY %1(<8 x s16>)97 RET_ReallyLR implicit $q098 99...100---101name: bswap_v4s32102alignment: 4103legalized: true104regBankSelected: true105tracksRegLiveness: true106machineFunctionInfo: {}107body: |108 bb.0:109 liveins: $q0110 111 ; CHECK-LABEL: name: bswap_v4s32112 ; CHECK: liveins: $q0113 ; CHECK-NEXT: {{ $}}114 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0115 ; CHECK-NEXT: [[REV32v16i8_:%[0-9]+]]:fpr128 = REV32v16i8 [[COPY]]116 ; CHECK-NEXT: $q0 = COPY [[REV32v16i8_]]117 ; CHECK-NEXT: RET_ReallyLR implicit $q0118 %0:fpr(<4 x s32>) = COPY $q0119 %1:fpr(<4 x s32>) = G_BSWAP %0120 $q0 = COPY %1(<4 x s32>)121 RET_ReallyLR implicit $q0122 123...124---125name: bswap_v2s32126alignment: 4127legalized: true128regBankSelected: true129tracksRegLiveness: true130machineFunctionInfo: {}131body: |132 bb.0:133 liveins: $d0134 135 ; CHECK-LABEL: name: bswap_v2s32136 ; CHECK: liveins: $d0137 ; CHECK-NEXT: {{ $}}138 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0139 ; CHECK-NEXT: [[REV32v8i8_:%[0-9]+]]:fpr64 = REV32v8i8 [[COPY]]140 ; CHECK-NEXT: $d0 = COPY [[REV32v8i8_]]141 ; CHECK-NEXT: RET_ReallyLR implicit $d0142 %0:fpr(<2 x s32>) = COPY $d0143 %1:fpr(<2 x s32>) = G_BSWAP %0144 $d0 = COPY %1(<2 x s32>)145 RET_ReallyLR implicit $d0146 147...148---149name: bswap_v2s64150alignment: 4151legalized: true152regBankSelected: true153tracksRegLiveness: true154machineFunctionInfo: {}155body: |156 bb.0:157 liveins: $q0158 159 ; CHECK-LABEL: name: bswap_v2s64160 ; CHECK: liveins: $q0161 ; CHECK-NEXT: {{ $}}162 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0163 ; CHECK-NEXT: [[REV64v16i8_:%[0-9]+]]:fpr128 = REV64v16i8 [[COPY]]164 ; CHECK-NEXT: $q0 = COPY [[REV64v16i8_]]165 ; CHECK-NEXT: RET_ReallyLR implicit $q0166 %0:fpr(<2 x s64>) = COPY $q0167 %1:fpr(<2 x s64>) = G_BSWAP %0168 $q0 = COPY %1(<2 x s64>)169 RET_ReallyLR implicit $q0170 171...172