288 lines · plain
1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s3---4name: test_f325alignment: 46exposesReturnsTwice: false7legalized: true8regBankSelected: true9selected: false10failedISel: false11tracksRegLiveness: true12body: |13 bb.0:14 liveins: $s0, $s1, $s2, $s315 16 ; CHECK-LABEL: name: test_f3217 ; CHECK: liveins: $s0, $s1, $s2, $s318 ; CHECK-NEXT: {{ $}}19 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $s020 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr32 = COPY $s121 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr32 = COPY $s222 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:fpr32 = COPY $s323 ; CHECK-NEXT: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF24 ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.ssub25 ; CHECK-NEXT: [[DEF1:%[0-9]+]]:fpr128 = IMPLICIT_DEF26 ; CHECK-NEXT: [[INSERT_SUBREG1:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF1]], [[COPY1]], %subreg.ssub27 ; CHECK-NEXT: [[INSvi32lane:%[0-9]+]]:fpr128 = INSvi32lane [[INSERT_SUBREG]], 1, [[INSERT_SUBREG1]], 028 ; CHECK-NEXT: [[DEF2:%[0-9]+]]:fpr128 = IMPLICIT_DEF29 ; CHECK-NEXT: [[INSERT_SUBREG2:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF2]], [[COPY2]], %subreg.ssub30 ; CHECK-NEXT: [[INSvi32lane1:%[0-9]+]]:fpr128 = INSvi32lane [[INSvi32lane]], 2, [[INSERT_SUBREG2]], 031 ; CHECK-NEXT: [[DEF3:%[0-9]+]]:fpr128 = IMPLICIT_DEF32 ; CHECK-NEXT: [[INSERT_SUBREG3:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF3]], [[COPY3]], %subreg.ssub33 ; CHECK-NEXT: [[INSvi32lane2:%[0-9]+]]:fpr128 = INSvi32lane [[INSvi32lane1]], 3, [[INSERT_SUBREG3]], 034 ; CHECK-NEXT: $q0 = COPY [[INSvi32lane2]]35 ; CHECK-NEXT: RET_ReallyLR implicit $q036 %0:fpr(s32) = COPY $s037 %1:fpr(s32) = COPY $s138 %2:fpr(s32) = COPY $s239 %3:fpr(s32) = COPY $s340 %4:fpr(<4 x s32>) = G_BUILD_VECTOR %0(s32), %1(s32), %2(s32), %3(s32)41 $q0 = COPY %4(<4 x s32>)42 RET_ReallyLR implicit $q043 44...45---46name: test_f6447alignment: 448exposesReturnsTwice: false49legalized: true50regBankSelected: true51selected: false52failedISel: false53tracksRegLiveness: true54body: |55 bb.0:56 liveins: $d0, $d1, $d2, $d357 58 ; CHECK-LABEL: name: test_f6459 ; CHECK: liveins: $d0, $d1, $d2, $d360 ; CHECK-NEXT: {{ $}}61 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d062 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d163 ; CHECK-NEXT: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF64 ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.dsub65 ; CHECK-NEXT: [[DEF1:%[0-9]+]]:fpr128 = IMPLICIT_DEF66 ; CHECK-NEXT: [[INSERT_SUBREG1:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF1]], [[COPY1]], %subreg.dsub67 ; CHECK-NEXT: [[INSvi64lane:%[0-9]+]]:fpr128 = INSvi64lane [[INSERT_SUBREG]], 1, [[INSERT_SUBREG1]], 068 ; CHECK-NEXT: $q0 = COPY [[INSvi64lane]]69 ; CHECK-NEXT: RET_ReallyLR implicit $q070 %0:fpr(s64) = COPY $d071 %1:fpr(s64) = COPY $d172 %4:fpr(<2 x s64>) = G_BUILD_VECTOR %0(s64), %1(s64)73 $q0 = COPY %4(<2 x s64>)74 RET_ReallyLR implicit $q075 76...77---78name: test_i3279alignment: 480exposesReturnsTwice: false81legalized: true82regBankSelected: true83selected: false84failedISel: false85tracksRegLiveness: true86body: |87 bb.0:88 liveins: $w0, $w1, $w2, $w389 90 ; CHECK-LABEL: name: test_i3291 ; CHECK: liveins: $w0, $w1, $w2, $w392 ; CHECK-NEXT: {{ $}}93 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32all = COPY $w094 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w195 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr32 = COPY $w296 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:gpr32 = COPY $w397 ; CHECK-NEXT: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF98 ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.ssub99 ; CHECK-NEXT: [[INSvi32gpr:%[0-9]+]]:fpr128 = INSvi32gpr [[INSERT_SUBREG]], 1, [[COPY1]]100 ; CHECK-NEXT: [[INSvi32gpr1:%[0-9]+]]:fpr128 = INSvi32gpr [[INSvi32gpr]], 2, [[COPY2]]101 ; CHECK-NEXT: [[INSvi32gpr2:%[0-9]+]]:fpr128 = INSvi32gpr [[INSvi32gpr1]], 3, [[COPY3]]102 ; CHECK-NEXT: $q0 = COPY [[INSvi32gpr2]]103 ; CHECK-NEXT: RET_ReallyLR implicit $q0104 %0:gpr(s32) = COPY $w0105 %1:gpr(s32) = COPY $w1106 %2:gpr(s32) = COPY $w2107 %3:gpr(s32) = COPY $w3108 %4:fpr(<4 x s32>) = G_BUILD_VECTOR %0(s32), %1(s32), %2(s32), %3(s32)109 $q0 = COPY %4(<4 x s32>)110 RET_ReallyLR implicit $q0111 112...113---114name: test_i64115alignment: 4116exposesReturnsTwice: false117legalized: true118regBankSelected: true119selected: false120failedISel: false121tracksRegLiveness: true122body: |123 bb.0:124 liveins: $x0, $x1125 126 ; CHECK-LABEL: name: test_i64127 ; CHECK: liveins: $x0, $x1128 ; CHECK-NEXT: {{ $}}129 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64all = COPY $x0130 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1131 ; CHECK-NEXT: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF132 ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.dsub133 ; CHECK-NEXT: [[INSvi64gpr:%[0-9]+]]:fpr128 = INSvi64gpr [[INSERT_SUBREG]], 1, [[COPY1]]134 ; CHECK-NEXT: $q0 = COPY [[INSvi64gpr]]135 ; CHECK-NEXT: RET_ReallyLR implicit $q0136 %0:gpr(s64) = COPY $x0137 %1:gpr(s64) = COPY $x1138 %4:fpr(<2 x s64>) = G_BUILD_VECTOR %0(s64), %1(s64)139 $q0 = COPY %4(<2 x s64>)140 RET_ReallyLR implicit $q0141 142...143---144name: test_p0145alignment: 4146exposesReturnsTwice: false147legalized: true148regBankSelected: true149selected: false150failedISel: false151tracksRegLiveness: true152body: |153 bb.0:154 liveins: $x0, $x1155 156 ; CHECK-LABEL: name: test_p0157 ; CHECK: liveins: $x0, $x1158 ; CHECK-NEXT: {{ $}}159 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64all = COPY $x0160 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1161 ; CHECK-NEXT: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF162 ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.dsub163 ; CHECK-NEXT: [[INSvi64gpr:%[0-9]+]]:fpr128 = INSvi64gpr [[INSERT_SUBREG]], 1, [[COPY1]]164 ; CHECK-NEXT: $q0 = COPY [[INSvi64gpr]]165 ; CHECK-NEXT: RET_ReallyLR implicit $q0166 %0:gpr(p0) = COPY $x0167 %1:gpr(p0) = COPY $x1168 %4:fpr(<2 x p0>) = G_BUILD_VECTOR %0(p0), %1(p0)169 $q0 = COPY %4(<2 x p0>)170 RET_ReallyLR implicit $q0171 172...173---174name: test_v4s32_zero175legalized: true176regBankSelected: true177tracksRegLiveness: true178liveins:179 - { reg: '$x0' }180frameInfo:181 maxAlignment: 1182machineFunctionInfo: {}183body: |184 bb.1:185 liveins: $x0186 187 ; CHECK-LABEL: name: test_v4s32_zero188 ; CHECK: liveins: $x0189 ; CHECK-NEXT: {{ $}}190 ; CHECK-NEXT: [[MOVIv2d_ns:%[0-9]+]]:fpr128 = MOVIv2d_ns 0191 ; CHECK-NEXT: $q0 = COPY [[MOVIv2d_ns]]192 ; CHECK-NEXT: RET_ReallyLR193 %0:gpr(p0) = COPY $x0194 %2:gpr(s32) = G_CONSTANT i32 0195 %3:fpr(s32) = COPY %2(s32)196 %4:fpr(s32) = COPY %2(s32)197 %5:fpr(s32) = COPY %2(s32)198 %6:fpr(s32) = COPY %2(s32)199 %1:fpr(<4 x s32>) = G_BUILD_VECTOR %3(s32), %4(s32), %5(s32), %6(s32)200 $q0 = COPY %1(<4 x s32>)201 RET_ReallyLR202...203---204name: test_v8s8_zero205legalized: true206regBankSelected: true207tracksRegLiveness: true208liveins:209 - { reg: '$x0' }210frameInfo:211 maxAlignment: 1212machineFunctionInfo: {}213body: |214 bb.1:215 liveins: $x0216 217 ; CHECK-LABEL: name: test_v8s8_zero218 ; CHECK: liveins: $x0219 ; CHECK-NEXT: {{ $}}220 ; CHECK-NEXT: [[MOVIv2d_ns:%[0-9]+]]:fpr128 = MOVIv2d_ns 0221 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY [[MOVIv2d_ns]].dsub222 ; CHECK-NEXT: $d0 = COPY [[COPY]]223 ; CHECK-NEXT: RET_ReallyLR224 %0:gpr(p0) = COPY $x0225 %2:gpr(s8) = G_CONSTANT i8 0226 %3:fpr(s8) = COPY %2(s8)227 %4:fpr(s8) = COPY %2(s8)228 %5:fpr(s8) = COPY %2(s8)229 %6:fpr(s8) = COPY %2(s8)230 %7:fpr(s8) = COPY %2(s8)231 %8:fpr(s8) = COPY %2(s8)232 %9:fpr(s8) = COPY %2(s8)233 %10:fpr(s8) = COPY %2(s8)234 %1:fpr(<8 x s8>) = G_BUILD_VECTOR %3(s8), %4(s8), %5(s8), %6(s8), %7(s8), %8(s8), %9(s8), %10(s8)235 $d0 = COPY %1(<8 x s8>)236 RET_ReallyLR237...238---239name: undef_elts_to_subreg_to_reg240legalized: true241regBankSelected: true242tracksRegLiveness: true243body: |244 bb.1:245 liveins: $s0246 ; We have a BUILD_VECTOR whose 0th element is a subregister of the wide247 ; register class. Everything else is undef. This is a SUBREG_TO_REG.248 249 ; CHECK-LABEL: name: undef_elts_to_subreg_to_reg250 ; CHECK: liveins: $s0251 ; CHECK-NEXT: {{ $}}252 ; CHECK-NEXT: %val:fpr32 = COPY $s0253 ; CHECK-NEXT: %bv:fpr128 = SUBREG_TO_REG 0, %val, %subreg.ssub254 ; CHECK-NEXT: $q0 = COPY %bv255 ; CHECK-NEXT: RET_ReallyLR implicit $q0256 %val:fpr(s32) = COPY $s0257 %undef:fpr(s32) = G_IMPLICIT_DEF258 %bv:fpr(<4 x s32>) = G_BUILD_VECTOR %val(s32), %undef(s32), %undef(s32), %undef(s32)259 $q0 = COPY %bv(<4 x s32>)260 RET_ReallyLR implicit $q0261...262...263---264name: undef_elts_different_regbanks265legalized: true266regBankSelected: true267tracksRegLiveness: true268body: |269 bb.1:270 liveins: $w0271 ; Element is not a subregister of the wide register class. This is not a272 ; SUBREG_TO_REG.273 274 ; CHECK-LABEL: name: undef_elts_different_regbanks275 ; CHECK: liveins: $w0276 ; CHECK-NEXT: {{ $}}277 ; CHECK-NEXT: %val:gpr32all = COPY $w0278 ; CHECK-NEXT: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF279 ; CHECK-NEXT: %bv:fpr128 = INSERT_SUBREG [[DEF]], %val, %subreg.ssub280 ; CHECK-NEXT: $q0 = COPY %bv281 ; CHECK-NEXT: RET_ReallyLR implicit $q0282 %val:gpr(s32) = COPY $w0283 %undef:gpr(s32) = G_IMPLICIT_DEF284 %bv:fpr(<4 x s32>) = G_BUILD_VECTOR %val(s32), %undef(s32), %undef(s32), %undef(s32)285 $q0 = COPY %bv(<4 x s32>)286 RET_ReallyLR implicit $q0287...288