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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s3---4name: cmp_imm_325legalized: true6regBankSelected: true7tracksRegLiveness: true8body: |9 bb.1:10 liveins: $w011 12 ; CHECK-LABEL: name: cmp_imm_3213 ; CHECK: liveins: $w014 ; CHECK-NEXT: {{ $}}15 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32sp = COPY $w016 ; CHECK-NEXT: [[SUBSWri:%[0-9]+]]:gpr32 = SUBSWri [[COPY]], 42, 0, implicit-def $nzcv17 ; CHECK-NEXT: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 1, implicit $nzcv18 ; CHECK-NEXT: $w0 = COPY [[CSINCWr]]19 ; CHECK-NEXT: RET_ReallyLR implicit $w020 %0:gpr(s32) = COPY $w021 %1:gpr(s32) = G_CONSTANT i32 4222 %5:gpr(s32) = G_ICMP intpred(eq), %0(s32), %123 $w0 = COPY %5(s32)24 RET_ReallyLR implicit $w025 26...27---28name: cmp_imm_6429legalized: true30regBankSelected: true31tracksRegLiveness: true32body: |33 bb.1:34 liveins: $x035 36 ; CHECK-LABEL: name: cmp_imm_6437 ; CHECK: liveins: $x038 ; CHECK-NEXT: {{ $}}39 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x040 ; CHECK-NEXT: [[SUBSXri:%[0-9]+]]:gpr64 = SUBSXri [[COPY]], 42, 0, implicit-def $nzcv41 ; CHECK-NEXT: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 1, implicit $nzcv42 ; CHECK-NEXT: $w0 = COPY [[CSINCWr]]43 ; CHECK-NEXT: RET_ReallyLR implicit $w044 %0:gpr(s64) = COPY $x045 %1:gpr(s64) = G_CONSTANT i64 4246 %5:gpr(s32) = G_ICMP intpred(eq), %0(s64), %147 $w0 = COPY %5(s32)48 RET_ReallyLR implicit $w049 50...51---52name: cmp_imm_out_of_range53legalized: true54regBankSelected: true55tracksRegLiveness: true56body: |57 bb.1:58 liveins: $x059 60 ; CHECK-LABEL: name: cmp_imm_out_of_range61 ; CHECK: liveins: $x062 ; CHECK-NEXT: {{ $}}63 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x064 ; CHECK-NEXT: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1313265 ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[MOVi32imm]], %subreg.sub_3266 ; CHECK-NEXT: [[SUBSXrr:%[0-9]+]]:gpr64 = SUBSXrr [[COPY]], [[SUBREG_TO_REG]], implicit-def $nzcv67 ; CHECK-NEXT: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 1, implicit $nzcv68 ; CHECK-NEXT: $w0 = COPY [[CSINCWr]]69 ; CHECK-NEXT: RET_ReallyLR implicit $w070 %0:gpr(s64) = COPY $x071 %1:gpr(s64) = G_CONSTANT i64 1313272 %5:gpr(s32) = G_ICMP intpred(eq), %0(s64), %173 $w0 = COPY %5(s32)74 RET_ReallyLR implicit $w075 76...77---78name: cmp_imm_lookthrough79legalized: true80regBankSelected: true81tracksRegLiveness: true82body: |83 bb.1:84 liveins: $w085 ; CHECK-LABEL: name: cmp_imm_lookthrough86 ; CHECK: liveins: $w087 ; CHECK-NEXT: {{ $}}88 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32sp = COPY $w089 ; CHECK-NEXT: [[SUBSWri:%[0-9]+]]:gpr32 = SUBSWri [[COPY]], 42, 0, implicit-def $nzcv90 ; CHECK-NEXT: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 1, implicit $nzcv91 ; CHECK-NEXT: $w0 = COPY [[CSINCWr]]92 ; CHECK-NEXT: RET_ReallyLR implicit $w093 %0:gpr(s32) = COPY $w094 %1:gpr(s64) = G_CONSTANT i64 4295 %2:gpr(s32) = G_TRUNC %1(s64)96 %5:gpr(s32) = G_ICMP intpred(eq), %0(s32), %297 $w0 = COPY %5(s32)98 RET_ReallyLR implicit $w099 100...101---102name: cmp_imm_lookthrough_bad_trunc103legalized: true104regBankSelected: true105tracksRegLiveness: true106body: |107 bb.1:108 liveins: $w0109 ; CHECK-LABEL: name: cmp_imm_lookthrough_bad_trunc110 ; CHECK: liveins: $w0111 ; CHECK-NEXT: {{ $}}112 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32sp = COPY $w0113 ; CHECK-NEXT: [[SUBSWri:%[0-9]+]]:gpr32 = SUBSWri [[COPY]], 0, 0, implicit-def $nzcv114 ; CHECK-NEXT: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 1, implicit $nzcv115 ; CHECK-NEXT: $w0 = COPY [[CSINCWr]]116 ; CHECK-NEXT: RET_ReallyLR implicit $w0117 %0:gpr(s32) = COPY $w0118 %1:gpr(s64) = G_CONSTANT i64 68719476736 ; 0x1000000000119 %2:gpr(s32) = G_TRUNC %1(s64) ; Value truncates to 0120 %5:gpr(s32) = G_ICMP intpred(eq), %0(s32), %2121 $w0 = COPY %5(s32)122 RET_ReallyLR implicit $w0123 124...125---126name: cmp_neg_imm_32127legalized: true128regBankSelected: true129tracksRegLiveness: true130body: |131 bb.1:132 liveins: $w0133 ; CHECK-LABEL: name: cmp_neg_imm_32134 ; CHECK: liveins: $w0135 ; CHECK-NEXT: {{ $}}136 ; CHECK-NEXT: %reg0:gpr32sp = COPY $w0137 ; CHECK-NEXT: [[ADDSWri:%[0-9]+]]:gpr32 = ADDSWri %reg0, 10, 0, implicit-def $nzcv138 ; CHECK-NEXT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 1, implicit $nzcv139 ; CHECK-NEXT: $w0 = COPY %cmp140 ; CHECK-NEXT: RET_ReallyLR implicit $w0141 %reg0:gpr(s32) = COPY $w0142 %cst:gpr(s32) = G_CONSTANT i32 -10143 %cmp:gpr(s32) = G_ICMP intpred(eq), %reg0(s32), %cst144 $w0 = COPY %cmp(s32)145 RET_ReallyLR implicit $w0146 147...148---149name: cmp_neg_imm_64150legalized: true151regBankSelected: true152tracksRegLiveness: true153body: |154 bb.1:155 liveins: $x0156 ; CHECK-LABEL: name: cmp_neg_imm_64157 ; CHECK: liveins: $x0158 ; CHECK-NEXT: {{ $}}159 ; CHECK-NEXT: %reg0:gpr64sp = COPY $x0160 ; CHECK-NEXT: [[ADDSXri:%[0-9]+]]:gpr64 = ADDSXri %reg0, 10, 0, implicit-def $nzcv161 ; CHECK-NEXT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 1, implicit $nzcv162 ; CHECK-NEXT: $w0 = COPY %cmp163 ; CHECK-NEXT: RET_ReallyLR implicit $w0164 %reg0:gpr(s64) = COPY $x0165 %cst:gpr(s64) = G_CONSTANT i64 -10166 %cmp:gpr(s32) = G_ICMP intpred(eq), %reg0(s64), %cst167 $w0 = COPY %cmp(s32)168 RET_ReallyLR implicit $w0169 170...171---172name: cmp_neg_imm_invalid173legalized: true174regBankSelected: true175tracksRegLiveness: true176body: |177 bb.1:178 liveins: $w0179 ; CHECK-LABEL: name: cmp_neg_imm_invalid180 ; CHECK: liveins: $w0181 ; CHECK-NEXT: {{ $}}182 ; CHECK-NEXT: %reg0:gpr32 = COPY $w0183 ; CHECK-NEXT: %cst:gpr32 = MOVi32imm -5000184 ; CHECK-NEXT: [[SUBSWrr:%[0-9]+]]:gpr32 = SUBSWrr %reg0, %cst, implicit-def $nzcv185 ; CHECK-NEXT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 1, implicit $nzcv186 ; CHECK-NEXT: $w0 = COPY %cmp187 ; CHECK-NEXT: RET_ReallyLR implicit $w0188 %reg0:gpr(s32) = COPY $w0189 %cst:gpr(s32) = G_CONSTANT i32 -5000190 %cmp:gpr(s32) = G_ICMP intpred(eq), %reg0(s32), %cst191 $w0 = COPY %cmp(s32)192 RET_ReallyLR implicit $w0193...194---195name: cmp_arith_extended_s64196legalized: true197regBankSelected: true198tracksRegLiveness: true199body: |200 bb.0:201 liveins: $w0, $x1202 203 ; CHECK-LABEL: name: cmp_arith_extended_s64204 ; CHECK: liveins: $w0, $x1205 ; CHECK-NEXT: {{ $}}206 ; CHECK-NEXT: %reg0:gpr32 = COPY $w0207 ; CHECK-NEXT: %reg1:gpr64sp = COPY $x1208 ; CHECK-NEXT: [[SUBSXrx:%[0-9]+]]:gpr64 = SUBSXrx %reg1, %reg0, 18, implicit-def $nzcv209 ; CHECK-NEXT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 9, implicit $nzcv210 ; CHECK-NEXT: $w0 = COPY %cmp211 ; CHECK-NEXT: RET_ReallyLR implicit $w0212 %reg0:gpr(s32) = COPY $w0213 %reg1:gpr(s64) = COPY $x1214 %ext:gpr(s64) = G_ZEXT %reg0(s32)215 %cst:gpr(s64) = G_CONSTANT i64 2216 %shift:gpr(s64) = G_SHL %ext, %cst(s64)217 %cmp:gpr(s32) = G_ICMP intpred(ugt), %reg1(s64), %shift218 $w0 = COPY %cmp(s32)219 RET_ReallyLR implicit $w0220 221...222---223name: cmp_arith_extended_s32224legalized: true225regBankSelected: true226tracksRegLiveness: true227body: |228 bb.0:229 liveins: $w0, $w1, $h0230 231 ; CHECK-LABEL: name: cmp_arith_extended_s32232 ; CHECK: liveins: $w0, $w1, $h0233 ; CHECK-NEXT: {{ $}}234 ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:fpr32 = SUBREG_TO_REG 0, $h0, %subreg.hsub235 ; CHECK-NEXT: %reg0:gpr32all = COPY [[SUBREG_TO_REG]]236 ; CHECK-NEXT: %reg1:gpr32sp = COPY $w1237 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY %reg0238 ; CHECK-NEXT: [[SUBSWrx:%[0-9]+]]:gpr32 = SUBSWrx %reg1, [[COPY]], 10, implicit-def $nzcv239 ; CHECK-NEXT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 9, implicit $nzcv240 ; CHECK-NEXT: $w0 = COPY %cmp241 ; CHECK-NEXT: RET_ReallyLR implicit $w0242 %reg0:gpr(s16) = COPY $h0243 %reg1:gpr(s32) = COPY $w1244 %ext:gpr(s32) = G_ZEXT %reg0(s16)245 %cst:gpr(s32) = G_CONSTANT i32 2246 %shift:gpr(s32) = G_SHL %ext, %cst(s32)247 %cmp:gpr(s32) = G_ICMP intpred(ugt), %reg1(s32), %shift248 $w0 = COPY %cmp(s32)249 RET_ReallyLR implicit $w0250 251...252---253name: cmp_arith_extended_shl_too_large254legalized: true255regBankSelected: true256tracksRegLiveness: true257body: |258 bb.0:259 liveins: $w0, $x1260 261 ; The constant on the G_SHL is > 4, so we won't sleect SUBSXrx262 263 ; CHECK-LABEL: name: cmp_arith_extended_shl_too_large264 ; CHECK: liveins: $w0, $x1265 ; CHECK-NEXT: {{ $}}266 ; CHECK-NEXT: %reg0:gpr32 = COPY $w0267 ; CHECK-NEXT: %reg1:gpr64 = COPY $x1268 ; CHECK-NEXT: [[ORRWrs:%[0-9]+]]:gpr32 = ORRWrs $wzr, %reg0, 0269 ; CHECK-NEXT: %ext:gpr64 = SUBREG_TO_REG 0, [[ORRWrs]], %subreg.sub_32270 ; CHECK-NEXT: [[SUBSXrs:%[0-9]+]]:gpr64 = SUBSXrs %reg1, %ext, 5, implicit-def $nzcv271 ; CHECK-NEXT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 9, implicit $nzcv272 ; CHECK-NEXT: $w0 = COPY %cmp273 ; CHECK-NEXT: RET_ReallyLR implicit $w0274 %reg0:gpr(s32) = COPY $w0275 %reg1:gpr(s64) = COPY $x1276 %ext:gpr(s64) = G_ZEXT %reg0(s32)277 %cst:gpr(s64) = G_CONSTANT i64 5278 %shift:gpr(s64) = G_SHL %ext, %cst(s64)279 %cmp:gpr(s32) = G_ICMP intpred(ugt), %reg1(s64), %shift280 $w0 = COPY %cmp(s32)281 RET_ReallyLR implicit $w0282 283...284---285name: cmp_add_rhs286legalized: true287regBankSelected: true288tracksRegLiveness: true289machineFunctionInfo: {}290body: |291 bb.0:292 liveins: $w0, $w1, $w2293 294 ; The CSINC should use the add's RHS.295 296 ; CHECK-LABEL: name: cmp_add_rhs297 ; CHECK: liveins: $w0, $w1, $w2298 ; CHECK-NEXT: {{ $}}299 ; CHECK-NEXT: %cmp_lhs:gpr32 = COPY $w0300 ; CHECK-NEXT: %cmp_rhs:gpr32 = COPY $w1301 ; CHECK-NEXT: %add_rhs:gpr32 = COPY $w2302 ; CHECK-NEXT: [[SUBSWrr:%[0-9]+]]:gpr32 = SUBSWrr %cmp_lhs, %cmp_rhs, implicit-def $nzcv303 ; CHECK-NEXT: %add:gpr32 = CSINCWr %add_rhs, %add_rhs, 1, implicit $nzcv304 ; CHECK-NEXT: $w0 = COPY %add305 ; CHECK-NEXT: RET_ReallyLR implicit $w0306 %cmp_lhs:gpr(s32) = COPY $w0307 %cmp_rhs:gpr(s32) = COPY $w1308 %add_rhs:gpr(s32) = COPY $w2309 %cmp:gpr(s32) = G_ICMP intpred(eq), %cmp_lhs(s32), %cmp_rhs310 %add:gpr(s32) = G_ADD %cmp, %add_rhs311 $w0 = COPY %add(s32)312 RET_ReallyLR implicit $w0313 314...315---316name: cmp_add_lhs317legalized: true318regBankSelected: true319tracksRegLiveness: true320machineFunctionInfo: {}321body: |322 bb.0:323 liveins: $w0, $w1, $w2324 325 ; The CSINC should use the add's LHS.326 327 ; CHECK-LABEL: name: cmp_add_lhs328 ; CHECK: liveins: $w0, $w1, $w2329 ; CHECK-NEXT: {{ $}}330 ; CHECK-NEXT: %cmp_lhs:gpr32 = COPY $w0331 ; CHECK-NEXT: %cmp_rhs:gpr32 = COPY $w1332 ; CHECK-NEXT: %add_lhs:gpr32 = COPY $w2333 ; CHECK-NEXT: [[SUBSWrr:%[0-9]+]]:gpr32 = SUBSWrr %cmp_lhs, %cmp_rhs, implicit-def $nzcv334 ; CHECK-NEXT: %add:gpr32 = CSINCWr %add_lhs, %add_lhs, 1, implicit $nzcv335 ; CHECK-NEXT: $w0 = COPY %add336 ; CHECK-NEXT: RET_ReallyLR implicit $w0337 %cmp_lhs:gpr(s32) = COPY $w0338 %cmp_rhs:gpr(s32) = COPY $w1339 %add_lhs:gpr(s32) = COPY $w2340 %cmp:gpr(s32) = G_ICMP intpred(eq), %cmp_lhs(s32), %cmp_rhs341 %add:gpr(s32) = G_ADD %add_lhs, %cmp342 $w0 = COPY %add(s32)343 RET_ReallyLR implicit $w0344 345...346---347name: cmp_add_lhs_vector348legalized: true349regBankSelected: true350tracksRegLiveness: true351machineFunctionInfo: {}352body: |353 bb.0:354 liveins: $q0, $q1, $q2355 356 ; We don't emit CSINC with vectors, so there should be no optimization here.357 358 ; CHECK-LABEL: name: cmp_add_lhs_vector359 ; CHECK: liveins: $q0, $q1, $q2360 ; CHECK-NEXT: {{ $}}361 ; CHECK-NEXT: %cmp_lhs:fpr128 = COPY $q0362 ; CHECK-NEXT: %cmp_rhs:fpr128 = COPY $q1363 ; CHECK-NEXT: %add_lhs:fpr128 = COPY $q2364 ; CHECK-NEXT: %cmp:fpr128 = CMEQv4i32 %cmp_lhs, %cmp_rhs365 ; CHECK-NEXT: %add:fpr128 = ADDv4i32 %add_lhs, %cmp366 ; CHECK-NEXT: $q0 = COPY %add367 ; CHECK-NEXT: RET_ReallyLR implicit $q0368 %cmp_lhs:fpr(<4 x s32>) = COPY $q0369 %cmp_rhs:fpr(<4 x s32>) = COPY $q1370 %add_lhs:fpr(<4 x s32>) = COPY $q2371 %cmp:fpr(<4 x s32>) = G_ICMP intpred(eq), %cmp_lhs(<4 x s32>), %cmp_rhs372 %add:fpr(<4 x s32>) = G_ADD %add_lhs, %cmp373 $q0 = COPY %add(<4 x s32>)374 RET_ReallyLR implicit $q0375 376...377---378name: cmp_add_rhs_64379legalized: true380regBankSelected: true381tracksRegLiveness: true382machineFunctionInfo: {}383body: |384 bb.0:385 liveins: $x0, $x1, $x2386 387 ; The CSINC should use the add's RHS.388 ; CHECK-LABEL: name: cmp_add_rhs_64389 ; CHECK: liveins: $x0, $x1, $x2390 ; CHECK-NEXT: {{ $}}391 ; CHECK-NEXT: %cmp_lhs:gpr64 = COPY $x0392 ; CHECK-NEXT: %cmp_rhs:gpr64 = COPY $x1393 ; CHECK-NEXT: %add_rhs:gpr64 = COPY $x2394 ; CHECK-NEXT: [[SUBSXrr:%[0-9]+]]:gpr64 = SUBSXrr %cmp_lhs, %cmp_rhs, implicit-def $nzcv395 ; CHECK-NEXT: %add:gpr64 = CSINCXr %add_rhs, %add_rhs, 1, implicit $nzcv396 ; CHECK-NEXT: $x0 = COPY %add397 ; CHECK-NEXT: RET_ReallyLR implicit $x0398 %cmp_lhs:gpr(s64) = COPY $x0399 %cmp_rhs:gpr(s64) = COPY $x1400 %add_rhs:gpr(s64) = COPY $x2401 %cmp:gpr(s32) = G_ICMP intpred(eq), %cmp_lhs(s64), %cmp_rhs402 %cmp_ext:gpr(s64) = G_ZEXT %cmp403 %add:gpr(s64) = G_ADD %cmp_ext, %add_rhs404 $x0 = COPY %add(s64)405 RET_ReallyLR implicit $x0406 407...408---409name: cmp_add_rhs_64_zext_multi_use410legalized: true411regBankSelected: true412tracksRegLiveness: true413machineFunctionInfo: {}414body: |415 bb.0:416 liveins: $x0, $x1, $x2417 418 ; The ZExt is used more than once so don't fold.419 ; CHECK-LABEL: name: cmp_add_rhs_64_zext_multi_use420 ; CHECK: liveins: $x0, $x1, $x2421 ; CHECK-NEXT: {{ $}}422 ; CHECK-NEXT: %cmp_lhs:gpr64 = COPY $x0423 ; CHECK-NEXT: %cmp_rhs:gpr64 = COPY $x1424 ; CHECK-NEXT: %add_rhs:gpr64 = COPY $x2425 ; CHECK-NEXT: [[SUBSXrr:%[0-9]+]]:gpr64 = SUBSXrr %cmp_lhs, %cmp_rhs, implicit-def $nzcv426 ; CHECK-NEXT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 1, implicit $nzcv427 ; CHECK-NEXT: [[ORRWrs:%[0-9]+]]:gpr32 = ORRWrs $wzr, %cmp, 0428 ; CHECK-NEXT: %cmp_ext:gpr64 = SUBREG_TO_REG 0, [[ORRWrs]], %subreg.sub_32429 ; CHECK-NEXT: %add:gpr64 = ADDXrr %cmp_ext, %add_rhs430 ; CHECK-NEXT: %or:gpr64 = ORRXrr %add, %cmp_ext431 ; CHECK-NEXT: $x0 = COPY %or432 ; CHECK-NEXT: RET_ReallyLR implicit $x0433 %cmp_lhs:gpr(s64) = COPY $x0434 %cmp_rhs:gpr(s64) = COPY $x1435 %add_rhs:gpr(s64) = COPY $x2436 %cmp:gpr(s32) = G_ICMP intpred(eq), %cmp_lhs(s64), %cmp_rhs437 %cmp_ext:gpr(s64) = G_ZEXT %cmp438 %add:gpr(s64) = G_ADD %cmp_ext, %add_rhs439 %or:gpr(s64) = G_OR %add, %cmp_ext440 $x0 = COPY %or(s64)441 RET_ReallyLR implicit $x0442 443...444---445name: cmp_add_rhs_64_cmp_multi_use446legalized: true447regBankSelected: true448tracksRegLiveness: true449machineFunctionInfo: {}450body: |451 bb.0:452 liveins: $x0, $x1, $x2453 454 ; The cmp is used more than once so don't fold.455 ; CHECK-LABEL: name: cmp_add_rhs_64_cmp_multi_use456 ; CHECK: liveins: $x0, $x1, $x2457 ; CHECK-NEXT: {{ $}}458 ; CHECK-NEXT: %cmp_lhs:gpr64 = COPY $x0459 ; CHECK-NEXT: %cmp_rhs:gpr64 = COPY $x1460 ; CHECK-NEXT: %add_rhs:gpr64 = COPY $x2461 ; CHECK-NEXT: [[SUBSXrr:%[0-9]+]]:gpr64 = SUBSXrr %cmp_lhs, %cmp_rhs, implicit-def $nzcv462 ; CHECK-NEXT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 1, implicit $nzcv463 ; CHECK-NEXT: [[ORRWrs:%[0-9]+]]:gpr32 = ORRWrs $wzr, %cmp, 0464 ; CHECK-NEXT: %cmp_ext:gpr64 = SUBREG_TO_REG 0, [[ORRWrs]], %subreg.sub_32465 ; CHECK-NEXT: %add:gpr64 = ADDXrr %cmp_ext, %add_rhs466 ; CHECK-NEXT: [[DEF:%[0-9]+]]:gpr64all = IMPLICIT_DEF467 ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:gpr64 = INSERT_SUBREG [[DEF]], %cmp, %subreg.sub_32468 ; CHECK-NEXT: %cmp_ext2:gpr64 = SBFMXri [[INSERT_SUBREG]], 0, 31469 ; CHECK-NEXT: %or:gpr64 = ORRXrr %add, %cmp_ext2470 ; CHECK-NEXT: $x0 = COPY %or471 ; CHECK-NEXT: RET_ReallyLR implicit $x0472 %cmp_lhs:gpr(s64) = COPY $x0473 %cmp_rhs:gpr(s64) = COPY $x1474 %add_rhs:gpr(s64) = COPY $x2475 %cmp:gpr(s32) = G_ICMP intpred(eq), %cmp_lhs(s64), %cmp_rhs476 %cmp_ext:gpr(s64) = G_ZEXT %cmp477 %add:gpr(s64) = G_ADD %cmp_ext, %add_rhs478 %cmp_ext2:gpr(s64) = G_SEXT %cmp479 %or:gpr(s64) = G_OR %add, %cmp_ext2480 $x0 = COPY %or(s64)481 RET_ReallyLR implicit $x0482