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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=aarch64-- -mattr=+lse -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s3 4--- |5 target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"6 7 define void @cmpxchg_i32(ptr %addr) { ret void }8 define void @cmpxchg_i64(ptr %addr) { ret void }9...10 11---12name: cmpxchg_i3213legalized: true14regBankSelected: true15 16body: |17 bb.0:18 liveins: $x019 20 ; CHECK-LABEL: name: cmpxchg_i3221 ; CHECK: liveins: $x022 ; CHECK-NEXT: {{ $}}23 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x024 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $wzr25 ; CHECK-NEXT: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 126 ; CHECK-NEXT: [[CASW:%[0-9]+]]:gpr32 = CASW [[COPY1]], [[MOVi32imm]], [[COPY]] :: (load store monotonic (s32) on %ir.addr)27 ; CHECK-NEXT: $w0 = COPY [[CASW]]28 %0:gpr(p0) = COPY $x029 %1:gpr(s32) = G_CONSTANT i32 030 %2:gpr(s32) = G_CONSTANT i32 131 %3:gpr(s32) = G_ATOMIC_CMPXCHG %0, %1, %2 :: (load store monotonic (s32) on %ir.addr)32 $w0 = COPY %3(s32)33...34 35---36name: cmpxchg_i6437legalized: true38regBankSelected: true39 40body: |41 bb.0:42 liveins: $x043 44 ; CHECK-LABEL: name: cmpxchg_i6445 ; CHECK: liveins: $x046 ; CHECK-NEXT: {{ $}}47 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x048 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64 = COPY $xzr49 ; CHECK-NEXT: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 150 ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[MOVi32imm]], %subreg.sub_3251 ; CHECK-NEXT: [[CASX:%[0-9]+]]:gpr64 = CASX [[COPY1]], [[SUBREG_TO_REG]], [[COPY]] :: (load store monotonic (s64) on %ir.addr)52 ; CHECK-NEXT: $x0 = COPY [[CASX]]53 %0:gpr(p0) = COPY $x054 %1:gpr(s64) = G_CONSTANT i64 055 %2:gpr(s64) = G_CONSTANT i64 156 %3:gpr(s64) = G_ATOMIC_CMPXCHG %0, %1, %2 :: (load store monotonic (s64) on %ir.addr)57 $x0 = COPY %3(s64)58...59