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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s3...4---5name: legal_v4s32_v2s326alignment: 47legalized: true8regBankSelected: true9tracksRegLiveness: true10registers:11 - { id: 0, class: fpr }12 - { id: 1, class: fpr }13 - { id: 2, class: fpr }14frameInfo:15 maxCallFrameSize: 016body: |17 bb.0:18 liveins: $d0, $d119 ; CHECK-LABEL: name: legal_v4s32_v2s3220 ; CHECK: liveins: $d0, $d121 ; CHECK-NEXT: {{ $}}22 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d023 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d124 ; CHECK-NEXT: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF25 ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY1]], %subreg.dsub26 ; CHECK-NEXT: [[DEF1:%[0-9]+]]:fpr128 = IMPLICIT_DEF27 ; CHECK-NEXT: [[INSERT_SUBREG1:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF1]], [[COPY]], %subreg.dsub28 ; CHECK-NEXT: [[INSvi64lane:%[0-9]+]]:fpr128 = INSvi64lane [[INSERT_SUBREG1]], 1, [[INSERT_SUBREG]], 029 ; CHECK-NEXT: $q0 = COPY [[INSvi64lane]]30 ; CHECK-NEXT: RET_ReallyLR implicit $q031 %0:fpr(<2 x s32>) = COPY $d032 %1:fpr(<2 x s32>) = COPY $d133 %2:fpr(<4 x s32>) = G_CONCAT_VECTORS %0(<2 x s32>), %1(<2 x s32>)34 $q0 = COPY %2(<4 x s32>)35 RET_ReallyLR implicit $q036 37...38---39name: legal_v8s16_v4s1640alignment: 441legalized: true42regBankSelected: true43tracksRegLiveness: true44registers:45 - { id: 0, class: fpr }46 - { id: 1, class: fpr }47 - { id: 2, class: fpr }48frameInfo:49 maxCallFrameSize: 050body: |51 bb.0:52 liveins: $d0, $d153 ; CHECK-LABEL: name: legal_v8s16_v4s1654 ; CHECK: liveins: $d0, $d155 ; CHECK-NEXT: {{ $}}56 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d057 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d158 ; CHECK-NEXT: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF59 ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY1]], %subreg.dsub60 ; CHECK-NEXT: [[DEF1:%[0-9]+]]:fpr128 = IMPLICIT_DEF61 ; CHECK-NEXT: [[INSERT_SUBREG1:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF1]], [[COPY]], %subreg.dsub62 ; CHECK-NEXT: [[INSvi64lane:%[0-9]+]]:fpr128 = INSvi64lane [[INSERT_SUBREG1]], 1, [[INSERT_SUBREG]], 063 ; CHECK-NEXT: $q0 = COPY [[INSvi64lane]]64 ; CHECK-NEXT: RET_ReallyLR implicit $q065 %0:fpr(<4 x s16>) = COPY $d066 %1:fpr(<4 x s16>) = COPY $d167 %2:fpr(<8 x s16>) = G_CONCAT_VECTORS %0(<4 x s16>), %1(<4 x s16>)68 $q0 = COPY %2(<8 x s16>)69 RET_ReallyLR implicit $q070 71...72---73name: select_v16s8_v8s8_undef74legalized: true75regBankSelected: true76tracksRegLiveness: true77body: |78 bb.0:79 liveins: $q080 81 ; CHECK-LABEL: name: select_v16s8_v8s8_undef82 ; CHECK: liveins: $q083 ; CHECK-NEXT: {{ $}}84 ; CHECK-NEXT: %a:fpr64 = IMPLICIT_DEF85 ; CHECK-NEXT: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF86 ; CHECK-NEXT: %concat:fpr128 = INSERT_SUBREG [[DEF]], %a, %subreg.dsub87 ; CHECK-NEXT: $q0 = COPY %concat88 ; CHECK-NEXT: RET_ReallyLR implicit $q089 %a:fpr(<8 x s8>) = G_IMPLICIT_DEF90 %b:fpr(<8 x s8>) = G_IMPLICIT_DEF91 %concat:fpr(<16 x s8>) = G_CONCAT_VECTORS %a(<8 x s8>), %b(<8 x s8>)92 $q0 = COPY %concat(<16 x s8>)93 RET_ReallyLR implicit $q094 95...96---97name: select_v16s8_v8s8_not_undef98legalized: true99regBankSelected: true100tracksRegLiveness: true101body: |102 bb.0:103 liveins: $q0, $d1104 ; CHECK-LABEL: name: select_v16s8_v8s8_not_undef105 ; CHECK: liveins: $q0, $d1106 ; CHECK-NEXT: {{ $}}107 ; CHECK-NEXT: %a:fpr64 = COPY $d0108 ; CHECK-NEXT: %b:fpr64 = COPY $d1109 ; CHECK-NEXT: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF110 ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], %b, %subreg.dsub111 ; CHECK-NEXT: [[DEF1:%[0-9]+]]:fpr128 = IMPLICIT_DEF112 ; CHECK-NEXT: [[INSERT_SUBREG1:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF1]], %a, %subreg.dsub113 ; CHECK-NEXT: %concat:fpr128 = INSvi64lane [[INSERT_SUBREG1]], 1, [[INSERT_SUBREG]], 0114 ; CHECK-NEXT: $q0 = COPY %concat115 ; CHECK-NEXT: RET_ReallyLR implicit $q0116 %a:fpr(<8 x s8>) = COPY $d0117 %b:fpr(<8 x s8>) = COPY $d1118 %concat:fpr(<16 x s8>) = G_CONCAT_VECTORS %a(<8 x s8>), %b(<8 x s8>)119 $q0 = COPY %concat(<16 x s8>)120 RET_ReallyLR implicit $q0121 122...123