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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s3---4name: test_constant_vec_pool_v2f645alignment: 46legalized: true7regBankSelected: true8tracksRegLiveness: true9liveins:10 - { reg: '$x0' }11frameInfo:12 maxAlignment: 113machineFunctionInfo: {}14body: |15 bb.1:16 liveins: $x017 18 ; CHECK-LABEL: name: test_constant_vec_pool_v2f6419 ; CHECK: liveins: $x020 ; CHECK-NEXT: {{ $}}21 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x022 ; CHECK-NEXT: [[ADRP:%[0-9]+]]:gpr64common = ADRP target-flags(aarch64-page) %const.023 ; CHECK-NEXT: [[LDRQui:%[0-9]+]]:fpr128 = LDRQui [[ADRP]], target-flags(aarch64-pageoff, aarch64-nc) %const.0 :: (load (s128) from constant-pool)24 ; CHECK-NEXT: STRQui [[LDRQui]], [[COPY]], 0 :: (store (<2 x s64>))25 ; CHECK-NEXT: RET_ReallyLR26 %0:gpr(p0) = COPY $x027 %3:fpr(s64) = G_FCONSTANT double 5.000000e-0128 %2:fpr(s64) = G_FCONSTANT double 1.600000e+0129 %1:fpr(<2 x s64>) = G_BUILD_VECTOR %2(s64), %3(s64)30 G_STORE %1(<2 x s64>), %0(p0) :: (store (<2 x s64>))31 RET_ReallyLR32 33...34---35name: test_constant_vec_pool_v4f3236alignment: 437legalized: true38regBankSelected: true39tracksRegLiveness: true40liveins:41 - { reg: '$x0' }42frameInfo:43 maxAlignment: 144body: |45 bb.1:46 liveins: $x047 48 ; CHECK-LABEL: name: test_constant_vec_pool_v4f3249 ; CHECK: liveins: $x050 ; CHECK-NEXT: {{ $}}51 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x052 ; CHECK-NEXT: [[ADRP:%[0-9]+]]:gpr64common = ADRP target-flags(aarch64-page) %const.053 ; CHECK-NEXT: [[LDRQui:%[0-9]+]]:fpr128 = LDRQui [[ADRP]], target-flags(aarch64-pageoff, aarch64-nc) %const.0 :: (load (s128) from constant-pool)54 ; CHECK-NEXT: STRQui [[LDRQui]], [[COPY]], 0 :: (store (<4 x s32>))55 ; CHECK-NEXT: RET_ReallyLR56 %0:gpr(p0) = COPY $x057 %3:fpr(s32) = G_FCONSTANT float 5.000000e-0158 %2:fpr(s32) = G_FCONSTANT float 1.600000e+0159 %1:fpr(<4 x s32>) = G_BUILD_VECTOR %2(s32), %3(s32), %3(s32), %3(s32)60 G_STORE %1(<4 x s32>), %0(p0) :: (store (<4 x s32>))61 RET_ReallyLR62 63...64---65name: test_constant_vec_pool_v2i6466alignment: 467legalized: true68regBankSelected: true69tracksRegLiveness: true70liveins:71 - { reg: '$x0' }72frameInfo:73 maxAlignment: 174body: |75 bb.1:76 liveins: $x077 78 ; CHECK-LABEL: name: test_constant_vec_pool_v2i6479 ; CHECK: liveins: $x080 ; CHECK-NEXT: {{ $}}81 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x082 ; CHECK-NEXT: [[ADRP:%[0-9]+]]:gpr64common = ADRP target-flags(aarch64-page) %const.083 ; CHECK-NEXT: [[LDRQui:%[0-9]+]]:fpr128 = LDRQui [[ADRP]], target-flags(aarch64-pageoff, aarch64-nc) %const.0 :: (load (s128) from constant-pool)84 ; CHECK-NEXT: STRQui [[LDRQui]], [[COPY]], 0 :: (store (<2 x s64>))85 ; CHECK-NEXT: RET_ReallyLR86 %0:gpr(p0) = COPY $x087 %3:gpr(s64) = G_CONSTANT i64 6783988 %2:gpr(s64) = G_CONSTANT i64 1237589 %1:fpr(<2 x s64>) = G_BUILD_VECTOR %2(s64), %3(s64)90 G_STORE %1(<2 x s64>), %0(p0) :: (store (<2 x s64>))91 RET_ReallyLR92 93...94---95name: test_constant_vec_pool_v4i3296alignment: 497legalized: true98regBankSelected: true99tracksRegLiveness: true100liveins:101 - { reg: '$x0' }102frameInfo:103 maxAlignment: 1104body: |105 bb.1:106 liveins: $x0107 108 ; CHECK-LABEL: name: test_constant_vec_pool_v4i32109 ; CHECK: liveins: $x0110 ; CHECK-NEXT: {{ $}}111 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0112 ; CHECK-NEXT: [[ADRP:%[0-9]+]]:gpr64common = ADRP target-flags(aarch64-page) %const.0113 ; CHECK-NEXT: [[LDRQui:%[0-9]+]]:fpr128 = LDRQui [[ADRP]], target-flags(aarch64-pageoff, aarch64-nc) %const.0 :: (load (s128) from constant-pool)114 ; CHECK-NEXT: STRQui [[LDRQui]], [[COPY]], 0 :: (store (<4 x s32>))115 ; CHECK-NEXT: RET_ReallyLR116 %0:gpr(p0) = COPY $x0117 %3:gpr(s32) = G_CONSTANT i32 67839118 %2:gpr(s32) = G_CONSTANT i32 12375119 %1:fpr(<4 x s32>) = G_BUILD_VECTOR %2(s32), %3(s32), %2(s32), %3(s32)120 G_STORE %1(<4 x s32>), %0(p0) :: (store (<4 x s32>))121 RET_ReallyLR122 123...124 125---126name: test_constant_vec_pool_v2i32127alignment: 4128legalized: true129regBankSelected: true130tracksRegLiveness: true131liveins:132 - { reg: '$x0' }133frameInfo:134 maxAlignment: 1135body: |136 bb.1:137 liveins: $x0138 139 ; CHECK-LABEL: name: test_constant_vec_pool_v2i32140 ; CHECK: liveins: $x0141 ; CHECK-NEXT: {{ $}}142 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0143 ; CHECK-NEXT: [[ADRP:%[0-9]+]]:gpr64common = ADRP target-flags(aarch64-page) %const.0144 ; CHECK-NEXT: [[LDRDui:%[0-9]+]]:fpr64 = LDRDui [[ADRP]], target-flags(aarch64-pageoff, aarch64-nc) %const.0 :: (load (s64) from constant-pool)145 ; CHECK-NEXT: STRDui [[LDRDui]], [[COPY]], 0 :: (store (<2 x s32>))146 ; CHECK-NEXT: RET_ReallyLR147 %0:gpr(p0) = COPY $x0148 %3:gpr(s32) = G_CONSTANT i32 67839149 %2:gpr(s32) = G_CONSTANT i32 12375150 %1:fpr(<2 x s32>) = G_BUILD_VECTOR %2(s32), %3(s32)151 G_STORE %1(<2 x s32>), %0(p0) :: (store (<2 x s32>))152 RET_ReallyLR153 154...155---156name: test_constant_all_zeros_v4f32157alignment: 4158legalized: true159regBankSelected: true160tracksRegLiveness: true161liveins:162 - { reg: '$x0' }163frameInfo:164 maxAlignment: 1165body: |166 bb.1:167 liveins: $x0168 169 ; CHECK-LABEL: name: test_constant_all_zeros_v4f32170 ; CHECK: liveins: $x0171 ; CHECK-NEXT: {{ $}}172 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0173 ; CHECK-NEXT: [[MOVIv2d_ns:%[0-9]+]]:fpr128 = MOVIv2d_ns 0174 ; CHECK-NEXT: STRQui [[MOVIv2d_ns]], [[COPY]], 0 :: (store (<4 x s32>))175 ; CHECK-NEXT: RET_ReallyLR176 %0:gpr(p0) = COPY $x0177 %2:fpr(s32) = G_FCONSTANT float 0.000000e+00178 %1:fpr(<4 x s32>) = G_BUILD_VECTOR %2(s32), %2(s32), %2(s32), %2(s32)179 G_STORE %1(<4 x s32>), %0(p0) :: (store (<4 x s32>))180 RET_ReallyLR181 182...183---184name: test_constant_all_ones_v4f32185alignment: 4186legalized: true187regBankSelected: true188tracksRegLiveness: true189liveins:190 - { reg: '$x0' }191frameInfo:192 maxAlignment: 1193body: |194 bb.1:195 liveins: $x0196 197 ; CHECK-LABEL: name: test_constant_all_ones_v4f32198 ; CHECK: liveins: $x0199 ; CHECK-NEXT: {{ $}}200 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0201 ; CHECK-NEXT: [[MOVIv2d_ns:%[0-9]+]]:fpr128 = MOVIv2d_ns 255202 ; CHECK-NEXT: STRQui [[MOVIv2d_ns]], [[COPY]], 0 :: (store (<4 x s32>))203 ; CHECK-NEXT: RET_ReallyLR204 %0:gpr(p0) = COPY $x0205 %2:fpr(s32) = G_FCONSTANT float 0xFFFFFFFFE0000000206 %1:fpr(<4 x s32>) = G_BUILD_VECTOR %2(s32), %2(s32), %2(s32), %2(s32)207 G_STORE %1(<4 x s32>), %0(p0) :: (store (<4 x s32>))208 RET_ReallyLR209 210...211