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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s3 4--- |5 target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"6 7 define i8 @const_s8() { ret i8 42 }8 define i16 @const_s16() { ret i16 42 }9 define i32 @const_s32() { ret i32 42 }10 define i64 @const_s64() { ret i64 1234567890123 }11 define i32 @const_s32_zero() { ret i32 0 }12 define i64 @const_s64_zero() { ret i64 0 }13 define ptr @const_p0_0() { ret ptr null }14 15 define i32 @fconst_s32() { ret i32 42 }16 define i64 @fconst_s64() { ret i64 1234567890123 }17 define float @fconst_s32_0() { ret float 0.0 }18 define double @fconst_s64_0() { ret double 0.0 }19 20 define void @optnone_i64() optnone noinline { ret void }21 define void @opt_i64() { ret void }22...23 24---25name: const_s826legalized: true27regBankSelected: true28body: |29 bb.0:30 ; CHECK-LABEL: name: const_s831 ; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 4232 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32all = COPY [[MOVi32imm]]33 ; CHECK-NEXT: $w0 = COPY [[COPY]]34 %0:gpr(s8) = G_CONSTANT i8 4235 %1:gpr(s32) = G_ANYEXT %0(s8)36 $w0 = COPY %1(s32)37...38 39---40name: const_s1641legalized: true42regBankSelected: true43body: |44 bb.0:45 ; CHECK-LABEL: name: const_s1646 ; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 4247 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32all = COPY [[MOVi32imm]]48 ; CHECK-NEXT: $w0 = COPY [[COPY]]49 %0:gpr(s16) = G_CONSTANT i16 4250 %1:gpr(s32) = G_ANYEXT %0(s16)51 $w0 = COPY %1(s32)52...53 54---55name: const_s3256legalized: true57regBankSelected: true58registers:59 - { id: 0, class: gpr }60 61body: |62 bb.0:63 ; CHECK-LABEL: name: const_s3264 ; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 4265 ; CHECK-NEXT: $w0 = COPY [[MOVi32imm]]66 %0(s32) = G_CONSTANT i32 4267 $w0 = COPY %0(s32)68...69 70---71name: const_s6472legalized: true73regBankSelected: true74registers:75 - { id: 0, class: gpr }76 77body: |78 bb.0:79 ; CHECK-LABEL: name: const_s6480 ; CHECK: [[MOVi64imm:%[0-9]+]]:gpr64 = MOVi64imm 123456789012381 ; CHECK-NEXT: $x0 = COPY [[MOVi64imm]]82 %0(s64) = G_CONSTANT i64 123456789012383 $x0 = COPY %0(s64)84...85 86---87name: const_s32_zero88legalized: true89regBankSelected: true90registers:91 - { id: 0, class: gpr }92 93body: |94 bb.0:95 ; CHECK-LABEL: name: const_s32_zero96 ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $wzr97 ; CHECK-NEXT: $w0 = COPY [[COPY]]98 %0(s32) = G_CONSTANT i32 099 $w0 = COPY %0(s32)100...101 102---103name: const_s64_zero104legalized: true105regBankSelected: true106registers:107 - { id: 0, class: gpr }108 109body: |110 bb.0:111 ; CHECK-LABEL: name: const_s64_zero112 ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $xzr113 ; CHECK-NEXT: $x0 = COPY [[COPY]]114 %0(s64) = G_CONSTANT i64 0115 $x0 = COPY %0(s64)116...117 118---119name: const_p0_0120legalized: true121regBankSelected: true122body: |123 bb.0:124 ; CHECK-LABEL: name: const_p0_0125 ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $xzr126 ; CHECK-NEXT: $x0 = COPY [[COPY]]127 %0:gpr(p0) = G_CONSTANT i64 0128 $x0 = COPY %0129...130 131---132name: fconst_s32133legalized: true134regBankSelected: true135registers:136 - { id: 0, class: fpr }137 138body: |139 bb.0:140 ; CHECK-LABEL: name: fconst_s32141 ; CHECK: [[FMOVSi:%[0-9]+]]:fpr32 = FMOVSi 12142 ; CHECK-NEXT: $s0 = COPY [[FMOVSi]]143 %0(s32) = G_FCONSTANT float 3.5144 $s0 = COPY %0(s32)145...146 147---148name: fconst_s64149legalized: true150regBankSelected: true151registers:152 - { id: 0, class: fpr }153 154body: |155 bb.0:156 ; CHECK-LABEL: name: fconst_s64157 ; CHECK: [[FMOVDi:%[0-9]+]]:fpr64 = FMOVDi 112158 ; CHECK-NEXT: $d0 = COPY [[FMOVDi]]159 %0(s64) = G_FCONSTANT double 1.0160 $d0 = COPY %0(s64)161...162 163---164name: fconst_s32_0165legalized: true166regBankSelected: true167registers:168 - { id: 0, class: fpr }169 170body: |171 bb.0:172 ; CHECK-LABEL: name: fconst_s32_0173 ; CHECK: [[FMOVS0_:%[0-9]+]]:fpr32 = FMOVS0174 ; CHECK-NEXT: $s0 = COPY [[FMOVS0_]]175 %0(s32) = G_FCONSTANT float 0.0176 $s0 = COPY %0(s32)177...178 179---180name: fconst_s64_0181legalized: true182regBankSelected: true183registers:184 - { id: 0, class: fpr }185 186body: |187 bb.0:188 ; CHECK-LABEL: name: fconst_s64_0189 ; CHECK: [[FMOVD0_:%[0-9]+]]:fpr64 = FMOVD0190 ; CHECK-NEXT: $x0 = COPY [[FMOVD0_]]191 %0(s64) = G_FCONSTANT double 0.0192 $x0 = COPY %0(s64)193...194---195name: optnone_i64196legalized: true197regBankSelected: true198body: |199 bb.0:200 ; CHECK-LABEL: name: optnone_i64201 ; CHECK: [[MOVi64imm:%[0-9]+]]:gpr64 = MOVi64imm 42202 ; CHECK-NEXT: $x0 = COPY [[MOVi64imm]]203 ; CHECK-NEXT: RET_ReallyLR implicit $x0204 %0:gpr(s64) = G_CONSTANT i64 42205 $x0 = COPY %0(s64)206 RET_ReallyLR implicit $x0207...208---209name: opt_i64210legalized: true211regBankSelected: true212body: |213 bb.0:214 ; CHECK-LABEL: name: opt_i64215 ; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 42216 ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64all = SUBREG_TO_REG 0, [[MOVi32imm]], %subreg.sub_32217 ; CHECK-NEXT: $x0 = COPY [[SUBREG_TO_REG]]218 ; CHECK-NEXT: RET_ReallyLR implicit $x0219 %0:gpr(s64) = G_CONSTANT i64 42220 $x0 = COPY %0(s64)221 RET_ReallyLR implicit $x0222...223