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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -O0 -mtriple=arm64-unknown-unknown -global-isel -run-pass=instruction-select -global-isel-abort=1 %s -o - | FileCheck %s3 4name: test_v8s85alignment: 46legalized: true7regBankSelected: true8tracksRegLiveness: true9body: |10 bb.0:11 liveins: $d012 13 ; CHECK-LABEL: name: test_v8s814 ; CHECK: liveins: $d015 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d016 ; CHECK: [[CLZv8i8_:%[0-9]+]]:fpr64 = CLZv8i8 [[COPY]]17 ; CHECK: $d0 = COPY [[CLZv8i8_]]18 ; CHECK: RET_ReallyLR implicit $d019 %0:fpr(<8 x s8>) = COPY $d020 %1:fpr(<8 x s8>) = G_CTLZ %0(<8 x s8>)21 $d0 = COPY %1(<8 x s8>)22 RET_ReallyLR implicit $d023 24...25---26name: test_v4s1627alignment: 428legalized: true29regBankSelected: true30tracksRegLiveness: true31body: |32 bb.0:33 liveins: $d034 35 ; CHECK-LABEL: name: test_v4s1636 ; CHECK: liveins: $d037 ; CHECK-NEXT: {{ $}}38 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d039 ; CHECK-NEXT: [[CLZv4i16_:%[0-9]+]]:fpr64 = CLZv4i16 [[COPY]]40 ; CHECK-NEXT: $d0 = COPY [[CLZv4i16_]]41 ; CHECK-NEXT: RET_ReallyLR implicit $d042 %0:fpr(<4 x s16>) = COPY $d043 %1:fpr(<4 x s16>) = G_CTLZ %0(<4 x s16>)44 $d0 = COPY %1(<4 x s16>)45 RET_ReallyLR implicit $d046 47...48---49name: test_v2s3250alignment: 451legalized: true52regBankSelected: true53tracksRegLiveness: true54body: |55 bb.0:56 liveins: $d057 58 ; CHECK-LABEL: name: test_v2s3259 ; CHECK: liveins: $d060 ; CHECK-NEXT: {{ $}}61 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d062 ; CHECK-NEXT: [[CLZv2i32_:%[0-9]+]]:fpr64 = CLZv2i32 [[COPY]]63 ; CHECK-NEXT: $d0 = COPY [[CLZv2i32_]]64 ; CHECK-NEXT: RET_ReallyLR implicit $d065 %0:fpr(<2 x s32>) = COPY $d066 %1:fpr(<2 x s32>) = G_CTLZ %0(<2 x s32>)67 $d0 = COPY %1(<2 x s32>)68 RET_ReallyLR implicit $d069 70...71---72name: test_s6473alignment: 474legalized: true75regBankSelected: true76tracksRegLiveness: true77body: |78 bb.0:79 liveins: $d080 81 ; CHECK-LABEL: name: test_s6482 ; CHECK: liveins: $d083 ; CHECK-NEXT: {{ $}}84 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d085 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64 = COPY [[COPY]]86 ; CHECK-NEXT: [[CLZXr:%[0-9]+]]:gpr64 = CLZXr [[COPY1]]87 ; CHECK-NEXT: $d0 = COPY [[CLZXr]]88 ; CHECK-NEXT: RET_ReallyLR implicit $d089 %0:fpr(s64) = COPY $d090 %2:gpr(s64) = COPY %0(s64)91 %1:gpr(s64) = G_CTLZ %2(s64)92 $d0 = COPY %1(s64)93 RET_ReallyLR implicit $d094 95...96---97name: test_s3298alignment: 499legalized: true100regBankSelected: true101tracksRegLiveness: true102body: |103 bb.0:104 liveins: $s0105 ; CHECK-LABEL: name: test_s32106 ; CHECK: liveins: $s0107 ; CHECK-NEXT: {{ $}}108 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $s0109 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY [[COPY]]110 ; CHECK-NEXT: [[CLZWr:%[0-9]+]]:gpr32 = CLZWr [[COPY1]]111 ; CHECK-NEXT: $s0 = COPY [[CLZWr]]112 ; CHECK-NEXT: RET_ReallyLR implicit $s0113 %0:fpr(s32) = COPY $s0114 %2:gpr(s32) = COPY %0(s32)115 %1:gpr(s32) = G_CTLZ %2(s32)116 $s0 = COPY %1(s32)117 RET_ReallyLR implicit $s0118 119...120---121name: test_v16s8122alignment: 4123legalized: true124regBankSelected: true125tracksRegLiveness: true126body: |127 bb.0:128 liveins: $q0129 130 ; CHECK-LABEL: name: test_v16s8131 ; CHECK: liveins: $q0132 ; CHECK-NEXT: {{ $}}133 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0134 ; CHECK-NEXT: [[CLZv16i8_:%[0-9]+]]:fpr128 = CLZv16i8 [[COPY]]135 ; CHECK-NEXT: $q0 = COPY [[CLZv16i8_]]136 ; CHECK-NEXT: RET_ReallyLR implicit $q0137 %0:fpr(<16 x s8>) = COPY $q0138 %1:fpr(<16 x s8>) = G_CTLZ %0(<16 x s8>)139 $q0 = COPY %1(<16 x s8>)140 RET_ReallyLR implicit $q0141 142...143---144name: test_v8s16145alignment: 4146legalized: true147regBankSelected: true148tracksRegLiveness: true149body: |150 bb.0:151 liveins: $q0152 153 ; CHECK-LABEL: name: test_v8s16154 ; CHECK: liveins: $q0155 ; CHECK-NEXT: {{ $}}156 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0157 ; CHECK-NEXT: [[CLZv8i16_:%[0-9]+]]:fpr128 = CLZv8i16 [[COPY]]158 ; CHECK-NEXT: $q0 = COPY [[CLZv8i16_]]159 ; CHECK-NEXT: RET_ReallyLR implicit $q0160 %0:fpr(<8 x s16>) = COPY $q0161 %1:fpr(<8 x s16>) = G_CTLZ %0(<8 x s16>)162 $q0 = COPY %1(<8 x s16>)163 RET_ReallyLR implicit $q0164 165...166---167name: test_v4s32168alignment: 4169legalized: true170regBankSelected: true171tracksRegLiveness: true172body: |173 bb.0:174 liveins: $q0175 176 ; CHECK-LABEL: name: test_v4s32177 ; CHECK: liveins: $q0178 ; CHECK-NEXT: {{ $}}179 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0180 ; CHECK-NEXT: [[CLZv4i32_:%[0-9]+]]:fpr128 = CLZv4i32 [[COPY]]181 ; CHECK-NEXT: $q0 = COPY [[CLZv4i32_]]182 ; CHECK-NEXT: RET_ReallyLR implicit $q0183 %0:fpr(<4 x s32>) = COPY $q0184 %1:fpr(<4 x s32>) = G_CTLZ %0(<4 x s32>)185 $q0 = COPY %1(<4 x s32>)186 RET_ReallyLR implicit $q0187 188...189