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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=aarch64 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s3#4# GPR variants should not use INSERT_SUBREG. FPR variants (DUP<ty>lane) should.5 6...7---8name: DUPv4i32gpr9legalized: true10regBankSelected: true11tracksRegLiveness: true12body: |13 bb.0.entry:14 liveins: $w015 ; CHECK-LABEL: name: DUPv4i32gpr16 ; CHECK: liveins: $w017 ; CHECK-NEXT: {{ $}}18 ; CHECK-NEXT: %copy:gpr32 = COPY $w019 ; CHECK-NEXT: %dup:fpr128 = DUPv4i32gpr %copy20 ; CHECK-NEXT: $q0 = COPY %dup21 ; CHECK-NEXT: RET_ReallyLR implicit $q022 %copy:gpr(s32) = COPY $w023 %dup:fpr(<4 x s32>) = G_DUP %copy(s32)24 $q0 = COPY %dup(<4 x s32>)25 RET_ReallyLR implicit $q026 27...28---29name: DUPv2i64gpr30alignment: 431legalized: true32regBankSelected: true33tracksRegLiveness: true34body: |35 bb.0.entry:36 liveins: $x037 ; CHECK-LABEL: name: DUPv2i64gpr38 ; CHECK: liveins: $x039 ; CHECK-NEXT: {{ $}}40 ; CHECK-NEXT: %copy:gpr64 = COPY $x041 ; CHECK-NEXT: %dup:fpr128 = DUPv2i64gpr %copy42 ; CHECK-NEXT: $q0 = COPY %dup43 ; CHECK-NEXT: RET_ReallyLR implicit $q044 %copy:gpr(s64) = COPY $x045 %dup:fpr(<2 x s64>) = G_DUP %copy(s64)46 $q0 = COPY %dup(<2 x s64>)47 RET_ReallyLR implicit $q048 49...50---51name: DUPv2i32gpr52alignment: 453legalized: true54regBankSelected: true55tracksRegLiveness: true56body: |57 bb.0.entry:58 liveins: $w059 ; CHECK-LABEL: name: DUPv2i32gpr60 ; CHECK: liveins: $w061 ; CHECK-NEXT: {{ $}}62 ; CHECK-NEXT: %copy:gpr32 = COPY $w063 ; CHECK-NEXT: %dup:fpr64 = DUPv2i32gpr %copy64 ; CHECK-NEXT: $d0 = COPY %dup65 ; CHECK-NEXT: RET_ReallyLR implicit $d066 %copy:gpr(s32) = COPY $w067 %dup:fpr(<2 x s32>) = G_DUP %copy(s32)68 $d0 = COPY %dup(<2 x s32>)69 RET_ReallyLR implicit $d070 71...72---73name: DUPv4i32lane74alignment: 475legalized: true76regBankSelected: true77tracksRegLiveness: true78body: |79 bb.0.entry:80 liveins: $s081 82 ; CHECK-LABEL: name: DUPv4i32lane83 ; CHECK: liveins: $s084 ; CHECK-NEXT: {{ $}}85 ; CHECK-NEXT: %copy:fpr32 = COPY $s086 ; CHECK-NEXT: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF87 ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], %copy, %subreg.ssub88 ; CHECK-NEXT: %dup:fpr128 = DUPv4i32lane [[INSERT_SUBREG]], 089 ; CHECK-NEXT: $q0 = COPY %dup90 ; CHECK-NEXT: RET_ReallyLR implicit $q091 %copy:fpr(s32) = COPY $s092 %dup:fpr(<4 x s32>) = G_DUP %copy(s32)93 $q0 = COPY %dup(<4 x s32>)94 RET_ReallyLR implicit $q095 96...97---98name: DUPv2i64lane99alignment: 4100legalized: true101regBankSelected: true102tracksRegLiveness: true103body: |104 bb.0.entry:105 liveins: $d0106 ; CHECK-LABEL: name: DUPv2i64lane107 ; CHECK: liveins: $d0108 ; CHECK-NEXT: {{ $}}109 ; CHECK-NEXT: %copy:fpr64 = COPY $d0110 ; CHECK-NEXT: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF111 ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], %copy, %subreg.dsub112 ; CHECK-NEXT: %dup:fpr128 = DUPv2i64lane [[INSERT_SUBREG]], 0113 ; CHECK-NEXT: $q0 = COPY %dup114 ; CHECK-NEXT: RET_ReallyLR implicit $q0115 %copy:fpr(s64) = COPY $d0116 %dup:fpr(<2 x s64>) = G_DUP %copy(s64)117 $q0 = COPY %dup(<2 x s64>)118 RET_ReallyLR implicit $q0119 120...121---122name: DUPv2i32lane123alignment: 4124legalized: true125regBankSelected: true126tracksRegLiveness: true127body: |128 bb.0.entry:129 liveins: $s0130 ; CHECK-LABEL: name: DUPv2i32lane131 ; CHECK: liveins: $s0132 ; CHECK-NEXT: {{ $}}133 ; CHECK-NEXT: %copy:fpr32 = COPY $s0134 ; CHECK-NEXT: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF135 ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], %copy, %subreg.ssub136 ; CHECK-NEXT: %dup:fpr64 = DUPv2i32lane [[INSERT_SUBREG]], 0137 ; CHECK-NEXT: $d0 = COPY %dup138 ; CHECK-NEXT: RET_ReallyLR implicit $d0139 %copy:fpr(s32) = COPY $s0140 %dup:fpr(<2 x s32>) = G_DUP %copy(s32)141 $d0 = COPY %dup(<2 x s32>)142 RET_ReallyLR implicit $d0143 144 145...146---147name: DUPv4i16lane148alignment: 4149legalized: true150regBankSelected: true151tracksRegLiveness: true152body: |153 bb.0.entry:154 liveins: $h0155 ; CHECK-LABEL: name: DUPv4i16lane156 ; CHECK: liveins: $h0157 ; CHECK-NEXT: {{ $}}158 ; CHECK-NEXT: %copy:fpr16 = COPY $h0159 ; CHECK-NEXT: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF160 ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], %copy, %subreg.hsub161 ; CHECK-NEXT: %dup:fpr64 = DUPv4i16lane [[INSERT_SUBREG]], 0162 ; CHECK-NEXT: $d0 = COPY %dup163 ; CHECK-NEXT: RET_ReallyLR implicit $d0164 %copy:fpr(s16) = COPY $h0165 %dup:fpr(<4 x s16>) = G_DUP %copy(s16)166 $d0 = COPY %dup(<4 x s16>)167 RET_ReallyLR implicit $d0168...169---170name: DUPv4i16gpr171alignment: 4172legalized: true173regBankSelected: true174tracksRegLiveness: true175body: |176 bb.0.entry:177 liveins: $w0178 ; CHECK-LABEL: name: DUPv4i16gpr179 ; CHECK: liveins: $w0180 ; CHECK-NEXT: {{ $}}181 ; CHECK-NEXT: %copy:gpr32 = COPY $w0182 ; CHECK-NEXT: %dup:fpr64 = DUPv4i16gpr %copy183 ; CHECK-NEXT: $d0 = COPY %dup184 ; CHECK-NEXT: RET_ReallyLR implicit $d0185 %copy:gpr(s32) = COPY $w0186 %dup:fpr(<4 x s16>) = G_DUP %copy(s32)187 $d0 = COPY %dup(<4 x s16>)188 RET_ReallyLR implicit $d0189 190...191---192name: DUPv8i16lane193alignment: 4194legalized: true195regBankSelected: true196tracksRegLiveness: true197body: |198 bb.0.entry:199 liveins: $h0200 ; CHECK-LABEL: name: DUPv8i16lane201 ; CHECK: liveins: $h0202 ; CHECK-NEXT: {{ $}}203 ; CHECK-NEXT: %copy:fpr16 = COPY $h0204 ; CHECK-NEXT: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF205 ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], %copy, %subreg.hsub206 ; CHECK-NEXT: %dup:fpr128 = DUPv8i16lane [[INSERT_SUBREG]], 0207 ; CHECK-NEXT: $q0 = COPY %dup208 ; CHECK-NEXT: RET_ReallyLR implicit $q0209 %copy:fpr(s16) = COPY $h0210 %dup:fpr(<8 x s16>) = G_DUP %copy(s16)211 $q0 = COPY %dup(<8 x s16>)212 RET_ReallyLR implicit $q0213 214...215---216name: DUPv8i16gpr217alignment: 4218legalized: true219regBankSelected: true220tracksRegLiveness: true221body: |222 bb.0.entry:223 liveins: $w0224 ; CHECK-LABEL: name: DUPv8i16gpr225 ; CHECK: liveins: $w0226 ; CHECK-NEXT: {{ $}}227 ; CHECK-NEXT: %copy:gpr32 = COPY $w0228 ; CHECK-NEXT: %dup:fpr128 = DUPv8i16gpr %copy229 ; CHECK-NEXT: $q0 = COPY %dup230 ; CHECK-NEXT: RET_ReallyLR implicit $q0231 %copy:gpr(s32) = COPY $w0232 %dup:fpr(<8 x s16>) = G_DUP %copy(s32)233 $q0 = COPY %dup(<8 x s16>)234 RET_ReallyLR implicit $q0235 236...237---238name: DUPv8i16gpr_s16_src239alignment: 4240legalized: true241regBankSelected: true242tracksRegLiveness: true243body: |244 bb.0.entry:245 liveins: $w0246 ; CHECK-LABEL: name: DUPv8i16gpr_s16_src247 ; CHECK: liveins: $w0248 ; CHECK-NEXT: {{ $}}249 ; CHECK-NEXT: %copy:gpr32 = COPY $w0250 ; CHECK-NEXT: %dup:fpr128 = DUPv8i16gpr %copy251 ; CHECK-NEXT: $q0 = COPY %dup252 ; CHECK-NEXT: RET_ReallyLR implicit $q0253 %copy:gpr(s32) = COPY $w0254 %trunc:gpr(s16) = G_TRUNC %copy255 %dup:fpr(<8 x s16>) = G_DUP %trunc(s16)256 $q0 = COPY %dup(<8 x s16>)257 RET_ReallyLR implicit $q0258 259...260---261name: DUPv4s16gpr_s16_src262alignment: 4263legalized: true264regBankSelected: true265tracksRegLiveness: true266body: |267 bb.0.entry:268 liveins: $w0269 ; CHECK-LABEL: name: DUPv4s16gpr_s16_src270 ; CHECK: liveins: $w0271 ; CHECK-NEXT: {{ $}}272 ; CHECK-NEXT: %copy:gpr32 = COPY $w0273 ; CHECK-NEXT: %dup:fpr64 = DUPv4i16gpr %copy274 ; CHECK-NEXT: $d0 = COPY %dup275 ; CHECK-NEXT: RET_ReallyLR implicit $d0276 %copy:gpr(s32) = COPY $w0277 %trunc:gpr(s16) = G_TRUNC %copy278 %dup:fpr(<4 x s16>) = G_DUP %trunc(s16)279 $d0 = COPY %dup(<4 x s16>)280 RET_ReallyLR implicit $d0281 282...283---284name: DUPv8i8gpr285alignment: 4286legalized: true287regBankSelected: true288tracksRegLiveness: true289body: |290 bb.0.entry:291 liveins: $w0292 ; CHECK-LABEL: name: DUPv8i8gpr293 ; CHECK: liveins: $w0294 ; CHECK-NEXT: {{ $}}295 ; CHECK-NEXT: %copy:gpr32 = COPY $w0296 ; CHECK-NEXT: %dup:fpr64 = DUPv8i8gpr %copy297 ; CHECK-NEXT: $d0 = COPY %dup298 ; CHECK-NEXT: RET_ReallyLR implicit $d0299 %copy:gpr(s32) = COPY $w0300 %dup:fpr(<8 x s8>) = G_DUP %copy(s32)301 $d0 = COPY %dup(<8 x s8>)302 RET_ReallyLR implicit $d0303 304...305---306name: DUPv8i8gpr_s8_src307alignment: 4308legalized: true309regBankSelected: true310tracksRegLiveness: true311body: |312 bb.0.entry:313 liveins: $w0314 ; CHECK-LABEL: name: DUPv8i8gpr_s8_src315 ; CHECK: liveins: $w0316 ; CHECK-NEXT: {{ $}}317 ; CHECK-NEXT: %copy:gpr32 = COPY $w0318 ; CHECK-NEXT: %dup:fpr64 = DUPv8i8gpr %copy319 ; CHECK-NEXT: $d0 = COPY %dup320 ; CHECK-NEXT: RET_ReallyLR implicit $d0321 %copy:gpr(s32) = COPY $w0322 %trunc:gpr(s8) = G_TRUNC %copy(s32)323 %dup:fpr(<8 x s8>) = G_DUP %trunc(s8)324 $d0 = COPY %dup(<8 x s8>)325 RET_ReallyLR implicit $d0326 327...328---329name: DUPv16i8gpr330alignment: 4331legalized: true332regBankSelected: true333tracksRegLiveness: true334body: |335 bb.0.entry:336 liveins: $w0337 ; CHECK-LABEL: name: DUPv16i8gpr338 ; CHECK: liveins: $w0339 ; CHECK-NEXT: {{ $}}340 ; CHECK-NEXT: %copy:gpr32 = COPY $w0341 ; CHECK-NEXT: %dup:fpr128 = DUPv16i8gpr %copy342 ; CHECK-NEXT: $q0 = COPY %dup343 ; CHECK-NEXT: RET_ReallyLR implicit $q0344 %copy:gpr(s32) = COPY $w0345 %dup:fpr(<16 x s8>) = G_DUP %copy(s32)346 $q0 = COPY %dup(<16 x s8>)347 RET_ReallyLR implicit $q0348...349---350name: DUPv16i8gpr_s8_src351alignment: 4352legalized: true353regBankSelected: true354tracksRegLiveness: true355body: |356 bb.0.entry:357 liveins: $w0358 ; CHECK-LABEL: name: DUPv16i8gpr_s8_src359 ; CHECK: liveins: $w0360 ; CHECK-NEXT: {{ $}}361 ; CHECK-NEXT: %copy:gpr32 = COPY $w0362 ; CHECK-NEXT: %dup:fpr128 = DUPv16i8gpr %copy363 ; CHECK-NEXT: $q0 = COPY %dup364 ; CHECK-NEXT: RET_ReallyLR implicit $q0365 %copy:gpr(s32) = COPY $w0366 %trunc:gpr(s8) = G_TRUNC %copy367 %dup:fpr(<16 x s8>) = G_DUP %trunc(s8)368 $q0 = COPY %dup(<16 x s8>)369 RET_ReallyLR implicit $q0370...371---372name: dup_v2p0373alignment: 4374legalized: true375regBankSelected: true376tracksRegLiveness: true377liveins:378 - { reg: '$x0' }379body: |380 bb.1:381 liveins: $x0382 383 ; CHECK-LABEL: name: dup_v2p0384 ; CHECK: liveins: $x0385 ; CHECK-NEXT: {{ $}}386 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64all = COPY $x0387 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64 = COPY [[COPY]]388 ; CHECK-NEXT: [[DUPv2i64gpr:%[0-9]+]]:fpr128 = DUPv2i64gpr [[COPY1]]389 ; CHECK-NEXT: $q0 = COPY [[DUPv2i64gpr]]390 ; CHECK-NEXT: RET_ReallyLR implicit $q0391 %0:gpr(p0) = COPY $x0392 %4:fpr(<2 x p0>) = G_DUP %0(p0)393 $q0 = COPY %4(<2 x p0>)394 RET_ReallyLR implicit $q0395 396...397---398name: cst_v4s32399legalized: true400regBankSelected: true401tracksRegLiveness: true402body: |403 bb.0.entry:404 liveins: $w0405 ; CHECK-LABEL: name: cst_v4s32406 ; CHECK: liveins: $w0407 ; CHECK-NEXT: {{ $}}408 ; CHECK-NEXT: %dup:fpr128 = MOVIv4i32 3, 0409 ; CHECK-NEXT: $q0 = COPY %dup410 ; CHECK-NEXT: RET_ReallyLR implicit $q0411 %cst:gpr(s32) = G_CONSTANT i32 3412 %dup:fpr(<4 x s32>) = G_DUP %cst(s32)413 $q0 = COPY %dup(<4 x s32>)414 RET_ReallyLR implicit $q0415 416...417---418name: cst_v8s8419legalized: true420regBankSelected: true421tracksRegLiveness: true422body: |423 bb.0.entry:424 liveins: $w0425 ; CHECK-LABEL: name: cst_v8s8426 ; CHECK: liveins: $w0427 ; CHECK-NEXT: {{ $}}428 ; CHECK-NEXT: %dup:fpr64 = MOVIv8b_ns 3429 ; CHECK-NEXT: $d0 = COPY %dup430 ; CHECK-NEXT: RET_ReallyLR implicit $d0431 %cst:gpr(s8) = G_CONSTANT i8 3432 %dup:fpr(<8 x s8>) = G_DUP %cst(s8)433 $d0 = COPY %dup(<8 x s8>)434 RET_ReallyLR implicit $d0435...436---437name: cst_v2p0438legalized: true439regBankSelected: true440tracksRegLiveness: true441body: |442 bb.0.entry:443 liveins: $w0444 ; CHECK-LABEL: name: cst_v2p0445 ; CHECK: liveins: $w0446 ; CHECK-NEXT: {{ $}}447 ; CHECK-NEXT: %cst:gpr64 = MOVi64imm 3448 ; CHECK-NEXT: [[ADRP:%[0-9]+]]:gpr64common = ADRP target-flags(aarch64-page) %const.0449 ; CHECK-NEXT: [[LDRQui:%[0-9]+]]:fpr128 = LDRQui [[ADRP]], target-flags(aarch64-pageoff, aarch64-nc) %const.0 :: (load (s128) from constant-pool)450 ; CHECK-NEXT: $q0 = COPY [[LDRQui]]451 ; CHECK-NEXT: RET_ReallyLR implicit $q0452 %cst:gpr(p0) = G_CONSTANT i64 3453 %dup:fpr(<2 x p0>) = G_DUP %cst(p0)454 $q0 = COPY %dup(<2 x p0>)455 RET_ReallyLR implicit $q0456...457---458name: cstv4i16gpri32459legalized: true460regBankSelected: true461tracksRegLiveness: true462body: |463 bb.0.entry:464 liveins:465 ; CHECK-LABEL: name: cstv4i16gpri32466 ; CHECK: %dup:fpr64 = MOVIv4i16 3, 0467 ; CHECK-NEXT: $d0 = COPY %dup468 ; CHECK-NEXT: RET_ReallyLR implicit $d0469 %cst:gpr(s32) = G_CONSTANT i32 3470 %dup:fpr(<4 x s16>) = G_DUP %cst(s32)471 $d0 = COPY %dup(<4 x s16>)472 RET_ReallyLR implicit $d0473 474...475