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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=aarch64 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s3#4# Test G_EXT selection using AArch64ext patterns.5 6...7---8name: v8s8_EXTv8i89alignment: 410legalized: true11regBankSelected: true12tracksRegLiveness: true13body: |14 bb.0:15 liveins: $d0, $d116 17 ; CHECK-LABEL: name: v8s8_EXTv8i818 ; CHECK: liveins: $d0, $d119 ; CHECK-NEXT: {{ $}}20 ; CHECK-NEXT: %v1:fpr64 = COPY $d021 ; CHECK-NEXT: %v2:fpr64 = COPY $d122 ; CHECK-NEXT: %shuf:fpr64 = EXTv8i8 %v1, %v2, 323 ; CHECK-NEXT: $d0 = COPY %shuf24 %v1:fpr(<8 x s8>) = COPY $d025 %v2:fpr(<8 x s8>) = COPY $d126 %3:gpr(s32) = G_CONSTANT i32 327 %shuf:fpr(<8 x s8>) = G_EXT %v1, %v2, %3(s32)28 $d0 = COPY %shuf29 30...31---32name: v16s8_EXTv16i833alignment: 434legalized: true35regBankSelected: true36tracksRegLiveness: true37body: |38 bb.0:39 liveins: $q0, $q140 41 ; CHECK-LABEL: name: v16s8_EXTv16i842 ; CHECK: liveins: $q0, $q143 ; CHECK-NEXT: {{ $}}44 ; CHECK-NEXT: %v1:fpr128 = COPY $q045 ; CHECK-NEXT: %v2:fpr128 = COPY $q146 ; CHECK-NEXT: %shuf:fpr128 = EXTv16i8 %v1, %v2, 347 ; CHECK-NEXT: $q0 = COPY %shuf48 %v1:fpr(<16 x s8>) = COPY $q049 %v2:fpr(<16 x s8>) = COPY $q150 %3:gpr(s32) = G_CONSTANT i32 351 %shuf:fpr(<16 x s8>) = G_EXT %v1, %v2, %3(s32)52 $q0 = COPY %shuf53 54...55---56name: v4s16_EXTv8i857alignment: 458legalized: true59regBankSelected: true60tracksRegLiveness: true61body: |62 bb.0:63 liveins: $d0, $d164 65 ; CHECK-LABEL: name: v4s16_EXTv8i866 ; CHECK: liveins: $d0, $d167 ; CHECK-NEXT: {{ $}}68 ; CHECK-NEXT: %v1:fpr64 = COPY $d069 ; CHECK-NEXT: %v2:fpr64 = COPY $d170 ; CHECK-NEXT: %shuf:fpr64 = EXTv8i8 %v1, %v2, 671 ; CHECK-NEXT: $d0 = COPY %shuf72 %v1:fpr(<4 x s16>) = COPY $d073 %v2:fpr(<4 x s16>) = COPY $d174 %3:gpr(s32) = G_CONSTANT i32 675 %shuf:fpr(<4 x s16>) = G_EXT %v1, %v2, %3(s32)76 $d0 = COPY %shuf77 78...79---80name: v8s16_EXTv16i881alignment: 482legalized: true83regBankSelected: true84tracksRegLiveness: true85body: |86 bb.0:87 liveins: $q0, $q188 89 ; CHECK-LABEL: name: v8s16_EXTv16i890 ; CHECK: liveins: $q0, $q191 ; CHECK-NEXT: {{ $}}92 ; CHECK-NEXT: %v1:fpr128 = COPY $q093 ; CHECK-NEXT: %v2:fpr128 = COPY $q194 ; CHECK-NEXT: %shuf:fpr128 = EXTv16i8 %v2, %v1, 1095 ; CHECK-NEXT: $q0 = COPY %shuf96 %v1:fpr(<8 x s16>) = COPY $q097 %v2:fpr(<8 x s16>) = COPY $q198 %3:gpr(s32) = G_CONSTANT i32 1099 %shuf:fpr(<8 x s16>) = G_EXT %v2, %v1, %3(s32)100 $q0 = COPY %shuf101...102 103...104---105name: v4s32_EXTv16i8106alignment: 4107legalized: true108regBankSelected: true109tracksRegLiveness: true110body: |111 bb.0:112 liveins: $q0, $q1113 114 ; CHECK-LABEL: name: v4s32_EXTv16i8115 ; CHECK: liveins: $q0, $q1116 ; CHECK-NEXT: {{ $}}117 ; CHECK-NEXT: %v1:fpr128 = COPY $q0118 ; CHECK-NEXT: %v2:fpr128 = COPY $q1119 ; CHECK-NEXT: %shuf:fpr128 = EXTv16i8 %v1, %v2, 12120 ; CHECK-NEXT: $q0 = COPY %shuf121 %v1:fpr(<4 x s32>) = COPY $q0122 %v2:fpr(<4 x s32>) = COPY $q1123 %3:gpr(s32) = G_CONSTANT i32 12124 %shuf:fpr(<4 x s32>) = G_EXT %v1, %v2, %3(s32)125 $q0 = COPY %shuf126 127...128---129name: v2s32_EXTv8i8130alignment: 4131legalized: true132regBankSelected: true133tracksRegLiveness: true134body: |135 bb.0:136 liveins: $d0, $d1137 138 ; CHECK-LABEL: name: v2s32_EXTv8i8139 ; CHECK: liveins: $d0, $d1140 ; CHECK-NEXT: {{ $}}141 ; CHECK-NEXT: %v1:fpr64 = COPY $d0142 ; CHECK-NEXT: %v2:fpr64 = COPY $d1143 ; CHECK-NEXT: %shuf:fpr64 = EXTv8i8 %v1, %v2, 2144 ; CHECK-NEXT: $d0 = COPY %shuf145 %v1:fpr(<2 x s32>) = COPY $d0146 %v2:fpr(<2 x s32>) = COPY $d1147 %3:gpr(s32) = G_CONSTANT i32 2148 %shuf:fpr(<2 x s32>) = G_EXT %v1, %v2, %3(s32)149 $d0 = COPY %shuf150 151...152---153name: v2s64_EXTv16i8154alignment: 4155legalized: true156regBankSelected: true157tracksRegLiveness: true158body: |159 bb.0:160 liveins: $q0, $q1161 162 ; CHECK-LABEL: name: v2s64_EXTv16i8163 ; CHECK: liveins: $q0, $q1164 ; CHECK-NEXT: {{ $}}165 ; CHECK-NEXT: %v1:fpr128 = COPY $q0166 ; CHECK-NEXT: %v2:fpr128 = COPY $q1167 ; CHECK-NEXT: %shuf:fpr128 = EXTv16i8 %v1, %v2, 2168 ; CHECK-NEXT: $q0 = COPY %shuf169 %v1:fpr(<2 x s64>) = COPY $q0170 %v2:fpr(<2 x s64>) = COPY $q1171 %3:gpr(s32) = G_CONSTANT i32 2172 %shuf:fpr(<2 x s64>) = G_EXT %v1, %v2, %3(s32)173 $q0 = COPY %shuf174...175