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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s3 4---5name: si646legalized: true7regBankSelected: true8tracksRegLiveness: true9body: |10 bb.0:11 liveins: $q0, $w012 13 ; CHECK-LABEL: name: si6414 ; CHECK: liveins: $q0, $w015 ; CHECK-NEXT: {{ $}}16 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q017 ; CHECK-NEXT: [[SMOVvi32to64_:%[0-9]+]]:gpr64 = SMOVvi32to64 [[COPY]], 118 ; CHECK-NEXT: $x0 = COPY [[SMOVvi32to64_]]19 ; CHECK-NEXT: RET_ReallyLR implicit $x020 %0:fpr(<4 x s32>) = COPY $q021 %3:gpr(s64) = G_CONSTANT i64 122 %2:fpr(s32) = G_EXTRACT_VECTOR_ELT %0(<4 x s32>), %3(s64)23 %5:gpr(s32) = COPY %2(s32)24 %4:gpr(s64) = G_SEXT %5(s32)25 $x0 = COPY %4(s64)26 RET_ReallyLR implicit $x027 28...29---30name: si64_231legalized: true32regBankSelected: true33tracksRegLiveness: true34body: |35 bb.0:36 liveins: $d0, $w037 38 ; CHECK-LABEL: name: si64_239 ; CHECK: liveins: $d0, $w040 ; CHECK-NEXT: {{ $}}41 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d042 ; CHECK-NEXT: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF43 ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.dsub44 ; CHECK-NEXT: [[SMOVvi32to64_:%[0-9]+]]:gpr64 = SMOVvi32to64 [[INSERT_SUBREG]], 145 ; CHECK-NEXT: $x0 = COPY [[SMOVvi32to64_]]46 ; CHECK-NEXT: RET_ReallyLR implicit $x047 %0:fpr(<2 x s32>) = COPY $d048 %3:gpr(s64) = G_CONSTANT i64 149 %2:fpr(s32) = G_EXTRACT_VECTOR_ELT %0(<2 x s32>), %3(s64)50 %5:gpr(s32) = COPY %2(s32)51 %4:gpr(s64) = G_SEXT %5(s32)52 $x0 = COPY %4(s64)53 RET_ReallyLR implicit $x054 55...56---57name: zi6458legalized: true59regBankSelected: true60tracksRegLiveness: true61body: |62 bb.0:63 liveins: $q0, $w064 65 ; CHECK-LABEL: name: zi6466 ; CHECK: liveins: $q0, $w067 ; CHECK-NEXT: {{ $}}68 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q069 ; CHECK-NEXT: [[UMOVvi32_:%[0-9]+]]:gpr32 = UMOVvi32 [[COPY]], 170 ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[UMOVvi32_]], %subreg.sub_3271 ; CHECK-NEXT: $x0 = COPY [[SUBREG_TO_REG]]72 ; CHECK-NEXT: RET_ReallyLR implicit $x073 %0:fpr(<4 x s32>) = COPY $q074 %3:gpr(s64) = G_CONSTANT i64 175 %2:fpr(s32) = G_EXTRACT_VECTOR_ELT %0(<4 x s32>), %3(s64)76 %5:gpr(s32) = COPY %2(s32)77 %4:gpr(s64) = G_ZEXT %5(s32)78 $x0 = COPY %4(s64)79 RET_ReallyLR implicit $x080 81...82---83name: zi64_284legalized: true85regBankSelected: true86tracksRegLiveness: true87body: |88 bb.0:89 liveins: $d0, $w090 91 ; CHECK-LABEL: name: zi64_292 ; CHECK: liveins: $d0, $w093 ; CHECK-NEXT: {{ $}}94 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d095 ; CHECK-NEXT: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF96 ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.dsub97 ; CHECK-NEXT: [[UMOVvi32_:%[0-9]+]]:gpr32 = UMOVvi32 [[INSERT_SUBREG]], 198 ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[UMOVvi32_]], %subreg.sub_3299 ; CHECK-NEXT: $x0 = COPY [[SUBREG_TO_REG]]100 ; CHECK-NEXT: RET_ReallyLR implicit $x0101 %0:fpr(<2 x s32>) = COPY $d0102 %3:gpr(s64) = G_CONSTANT i64 1103 %2:fpr(s32) = G_EXTRACT_VECTOR_ELT %0(<2 x s32>), %3(s64)104 %5:gpr(s32) = COPY %2(s32)105 %4:gpr(s64) = G_ZEXT %5(s32)106 $x0 = COPY %4(s64)107 RET_ReallyLR implicit $x0108 109...110---111name: si32112legalized: true113regBankSelected: true114tracksRegLiveness: true115body: |116 bb.0:117 liveins: $q0, $w0118 119 ; CHECK-LABEL: name: si32120 ; CHECK: liveins: $q0, $w0121 ; CHECK-NEXT: {{ $}}122 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0123 ; CHECK-NEXT: [[SMOVvi16to32_:%[0-9]+]]:gpr32 = SMOVvi16to32 [[COPY]], 1124 ; CHECK-NEXT: $w0 = COPY [[SMOVvi16to32_]]125 ; CHECK-NEXT: RET_ReallyLR implicit $w0126 %0:fpr(<8 x s16>) = COPY $q0127 %4:gpr(s64) = G_CONSTANT i64 1128 %3:fpr(s16) = G_EXTRACT_VECTOR_ELT %0(<8 x s16>), %4(s64)129 %6:gpr(s16) = COPY %3(s16)130 %5:gpr(s32) = G_SEXT %6(s16)131 $w0 = COPY %5(s32)132 RET_ReallyLR implicit $w0133 134...135---136name: zi32137legalized: true138regBankSelected: true139tracksRegLiveness: true140body: |141 bb.0:142 liveins: $q0, $w0143 144 ; CHECK-LABEL: name: zi32145 ; CHECK: liveins: $q0, $w0146 ; CHECK-NEXT: {{ $}}147 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0148 ; CHECK-NEXT: [[UMOVvi16_:%[0-9]+]]:gpr32 = UMOVvi16 [[COPY]], 1149 ; CHECK-NEXT: $w0 = COPY [[UMOVvi16_]]150 ; CHECK-NEXT: RET_ReallyLR implicit $w0151 %0:fpr(<8 x s16>) = COPY $q0152 %4:gpr(s64) = G_CONSTANT i64 1153 %3:fpr(s16) = G_EXTRACT_VECTOR_ELT %0(<8 x s16>), %4(s64)154 %6:gpr(s16) = COPY %3(s16)155 %5:gpr(s32) = G_ZEXT %6(s16)156 $w0 = COPY %5(s32)157 RET_ReallyLR implicit $w0158 159...160---161name: si32_2162legalized: true163regBankSelected: true164tracksRegLiveness: true165body: |166 bb.0:167 liveins: $d0, $w0168 169 ; CHECK-LABEL: name: si32_2170 ; CHECK: liveins: $d0, $w0171 ; CHECK-NEXT: {{ $}}172 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0173 ; CHECK-NEXT: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF174 ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.dsub175 ; CHECK-NEXT: [[SMOVvi16to32_:%[0-9]+]]:gpr32 = SMOVvi16to32 [[INSERT_SUBREG]], 1176 ; CHECK-NEXT: $w0 = COPY [[SMOVvi16to32_]]177 ; CHECK-NEXT: RET_ReallyLR implicit $w0178 %0:fpr(<4 x s16>) = COPY $d0179 %4:gpr(s64) = G_CONSTANT i64 1180 %3:fpr(s16) = G_EXTRACT_VECTOR_ELT %0(<4 x s16>), %4(s64)181 %6:gpr(s16) = COPY %3(s16)182 %5:gpr(s32) = G_SEXT %6(s16)183 $w0 = COPY %5(s32)184 RET_ReallyLR implicit $w0185 186...187---188name: zi32_2189legalized: true190regBankSelected: true191tracksRegLiveness: true192body: |193 bb.0:194 liveins: $d0, $w0195 196 ; CHECK-LABEL: name: zi32_2197 ; CHECK: liveins: $d0, $w0198 ; CHECK-NEXT: {{ $}}199 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0200 ; CHECK-NEXT: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF201 ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.dsub202 ; CHECK-NEXT: [[UMOVvi16_:%[0-9]+]]:gpr32 = UMOVvi16 [[INSERT_SUBREG]], 1203 ; CHECK-NEXT: $w0 = COPY [[UMOVvi16_]]204 ; CHECK-NEXT: RET_ReallyLR implicit $w0205 %0:fpr(<4 x s16>) = COPY $d0206 %4:gpr(s64) = G_CONSTANT i64 1207 %3:fpr(s16) = G_EXTRACT_VECTOR_ELT %0(<4 x s16>), %4(s64)208 %6:gpr(s16) = COPY %3(s16)209 %5:gpr(s32) = G_ZEXT %6(s16)210 $w0 = COPY %5(s32)211 RET_ReallyLR implicit $w0212 213...214---215name: si16216legalized: true217regBankSelected: true218tracksRegLiveness: true219body: |220 bb.0:221 liveins: $q0, $w0222 223 ; CHECK-LABEL: name: si16224 ; CHECK: liveins: $q0, $w0225 ; CHECK-NEXT: {{ $}}226 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0227 ; CHECK-NEXT: [[SMOVvi8to32_:%[0-9]+]]:gpr32 = SMOVvi8to32 [[COPY]], 1228 ; CHECK-NEXT: $w0 = COPY [[SMOVvi8to32_]]229 ; CHECK-NEXT: RET_ReallyLR implicit $w0230 %0:fpr(<16 x s8>) = COPY $q0231 %4:gpr(s64) = G_CONSTANT i64 1232 %3:fpr(s8) = G_EXTRACT_VECTOR_ELT %0(<16 x s8>), %4(s64)233 %7:gpr(s8) = COPY %3(s8)234 %6:gpr(s32) = G_SEXT %7(s8)235 $w0 = COPY %6(s32)236 RET_ReallyLR implicit $w0237...238---239name: zi16240legalized: true241regBankSelected: true242tracksRegLiveness: true243body: |244 bb.0:245 liveins: $q0, $w0246 247 ; CHECK-LABEL: name: zi16248 ; CHECK: liveins: $q0, $w0249 ; CHECK-NEXT: {{ $}}250 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0251 ; CHECK-NEXT: [[UMOVvi8_:%[0-9]+]]:gpr32 = UMOVvi8 [[COPY]], 1252 ; CHECK-NEXT: $w0 = COPY [[UMOVvi8_]]253 ; CHECK-NEXT: RET_ReallyLR implicit $w0254 %0:fpr(<16 x s8>) = COPY $q0255 %4:gpr(s64) = G_CONSTANT i64 1256 %3:fpr(s8) = G_EXTRACT_VECTOR_ELT %0(<16 x s8>), %4(s64)257 %7:gpr(s8) = COPY %3(s8)258 %6:gpr(s32) = G_ZEXT %7(s8)259 $w0 = COPY %6(s32)260 RET_ReallyLR implicit $w0261 262...263---264name: si16_2265legalized: true266regBankSelected: true267tracksRegLiveness: true268body: |269 bb.0:270 liveins: $d0, $w0271 272 ; CHECK-LABEL: name: si16_2273 ; CHECK: liveins: $d0, $w0274 ; CHECK-NEXT: {{ $}}275 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0276 ; CHECK-NEXT: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF277 ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.dsub278 ; CHECK-NEXT: [[SMOVvi8to32_:%[0-9]+]]:gpr32 = SMOVvi8to32 [[INSERT_SUBREG]], 1279 ; CHECK-NEXT: $w0 = COPY [[SMOVvi8to32_]]280 ; CHECK-NEXT: RET_ReallyLR implicit $w0281 %0:fpr(<8 x s8>) = COPY $d0282 %4:gpr(s64) = G_CONSTANT i64 1283 %3:fpr(s8) = G_EXTRACT_VECTOR_ELT %0(<8 x s8>), %4(s64)284 %7:gpr(s8) = COPY %3(s8)285 %6:gpr(s32) = G_SEXT %7(s8)286 $w0 = COPY %6(s32)287 RET_ReallyLR implicit $w0288...289---290name: zi16_2291legalized: true292regBankSelected: true293tracksRegLiveness: true294body: |295 bb.0:296 liveins: $d0, $w0297 298 ; CHECK-LABEL: name: zi16_2299 ; CHECK: liveins: $d0, $w0300 ; CHECK-NEXT: {{ $}}301 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0302 ; CHECK-NEXT: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF303 ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.dsub304 ; CHECK-NEXT: [[UMOVvi8_:%[0-9]+]]:gpr32 = UMOVvi8 [[INSERT_SUBREG]], 1305 ; CHECK-NEXT: $w0 = COPY [[UMOVvi8_]]306 ; CHECK-NEXT: RET_ReallyLR implicit $w0307 %0:fpr(<8 x s8>) = COPY $d0308 %4:gpr(s64) = G_CONSTANT i64 1309 %3:fpr(s8) = G_EXTRACT_VECTOR_ELT %0(<8 x s8>), %4(s64)310 %7:gpr(s8) = COPY %3(s8)311 %6:gpr(s32) = G_ZEXT %7(s8)312 $w0 = COPY %6(s32)313 RET_ReallyLR implicit $w0314 315...316---317name: skip_anyext_to_16318legalized: true319regBankSelected: true320tracksRegLiveness: true321body: |322 bb.1.entry:323 ; CHECK-LABEL: name: skip_anyext_to_16324 ; CHECK: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF325 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr8 = COPY [[DEF]].bsub326 ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:fpr32 = SUBREG_TO_REG 0, [[COPY]], %subreg.bsub327 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32all = COPY [[SUBREG_TO_REG]]328 ; CHECK-NEXT: $w0 = COPY [[COPY1]]329 %5:fpr(<16 x s8>) = G_IMPLICIT_DEF330 %12:gpr(s64) = G_CONSTANT i64 0331 %4:fpr(s8) = G_EXTRACT_VECTOR_ELT %5(<16 x s8>), %12(s64)332 %11:gpr(s8) = COPY %4(s8)333 %8:gpr(s16) = G_ANYEXT %11(s8)334 %ext:gpr(s32) = G_ANYEXT %8(s16)335 $w0 = COPY %ext(s32)336...337