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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=aarch64-unknown-unknown -verify-machineinstrs -O0 -run-pass=instruction-select -global-isel-abort=1 %s -o - | FileCheck %s3...4---5name: v2s32_fpr6alignment: 47legalized: true8regBankSelected: true9tracksRegLiveness: true10registers:11 - { id: 0, class: fpr }12 - { id: 1, class: fpr }13 - { id: 2, class: gpr }14 - { id: 3, class: fpr }15body: |16 bb.0:17 liveins: $d018 19 ; CHECK-LABEL: name: v2s32_fpr20 ; CHECK: liveins: $d021 ; CHECK-NEXT: {{ $}}22 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d023 ; CHECK-NEXT: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF24 ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.dsub25 ; CHECK-NEXT: [[DUPi32_:%[0-9]+]]:fpr32 = DUPi32 [[INSERT_SUBREG]], 126 ; CHECK-NEXT: $s0 = COPY [[DUPi32_]]27 ; CHECK-NEXT: RET_ReallyLR implicit $s028 %0:fpr(<2 x s32>) = COPY $d029 %2:gpr(s64) = G_CONSTANT i64 130 %3:fpr(s64) = COPY %2(s64)31 %1:fpr(s32) = G_EXTRACT_VECTOR_ELT %0(<2 x s32>), %3(s64)32 $s0 = COPY %1(s32)33 RET_ReallyLR implicit $s034 35...36---37name: v2s32_fpr_idx038alignment: 439legalized: true40regBankSelected: true41tracksRegLiveness: true42body: |43 bb.0:44 liveins: $d045 ; CHECK-LABEL: name: v2s32_fpr_idx046 ; CHECK: liveins: $d047 ; CHECK-NEXT: {{ $}}48 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d049 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr32 = COPY [[COPY]].ssub50 ; CHECK-NEXT: $s0 = COPY [[COPY1]]51 ; CHECK-NEXT: RET_ReallyLR implicit $s052 %0:fpr(<2 x s32>) = COPY $d053 %2:gpr(s64) = G_CONSTANT i64 054 %3:fpr(s64) = COPY %2(s64)55 %1:fpr(s32) = G_EXTRACT_VECTOR_ELT %0(<2 x s32>), %3(s64)56 $s0 = COPY %1(s32)57 RET_ReallyLR implicit $s058 59...60---61name: v2s64_fpr62alignment: 463legalized: true64regBankSelected: true65tracksRegLiveness: true66registers:67 - { id: 0, class: fpr }68 - { id: 1, class: fpr }69 - { id: 2, class: gpr }70 - { id: 3, class: fpr }71body: |72 bb.0:73 liveins: $q074 75 ; CHECK-LABEL: name: v2s64_fpr76 ; CHECK: liveins: $q077 ; CHECK-NEXT: {{ $}}78 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q079 ; CHECK-NEXT: [[DUPi64_:%[0-9]+]]:fpr64 = DUPi64 [[COPY]], 280 ; CHECK-NEXT: $d0 = COPY [[DUPi64_]]81 ; CHECK-NEXT: RET_ReallyLR implicit $d082 %0:fpr(<2 x s64>) = COPY $q083 %2:gpr(s64) = G_CONSTANT i64 284 %3:fpr(s64) = COPY %2(s64)85 %1:fpr(s64) = G_EXTRACT_VECTOR_ELT %0(<2 x s64>), %3(s64)86 $d0 = COPY %1(s64)87 RET_ReallyLR implicit $d088 89...90---91name: v4s16_fpr92alignment: 493legalized: true94regBankSelected: true95tracksRegLiveness: true96registers:97 - { id: 0, class: fpr }98 - { id: 1, class: fpr }99 - { id: 2, class: gpr }100 - { id: 3, class: fpr }101body: |102 bb.0:103 liveins: $d0104 105 ; CHECK-LABEL: name: v4s16_fpr106 ; CHECK: liveins: $d0107 ; CHECK-NEXT: {{ $}}108 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0109 ; CHECK-NEXT: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF110 ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.dsub111 ; CHECK-NEXT: [[DUPi16_:%[0-9]+]]:fpr16 = DUPi16 [[INSERT_SUBREG]], 1112 ; CHECK-NEXT: $h0 = COPY [[DUPi16_]]113 ; CHECK-NEXT: RET_ReallyLR implicit $h0114 %0:fpr(<4 x s16>) = COPY $d0115 %2:gpr(s64) = G_CONSTANT i64 1116 %3:fpr(s64) = COPY %2(s64)117 %1:fpr(s16) = G_EXTRACT_VECTOR_ELT %0(<4 x s16>), %3(s64)118 $h0 = COPY %1(s16)119 RET_ReallyLR implicit $h0120 121...122---123name: v8s16_fpr124alignment: 4125legalized: true126regBankSelected: true127tracksRegLiveness: true128body: |129 bb.0:130 liveins: $q0131 ; CHECK-LABEL: name: v8s16_fpr132 ; CHECK: liveins: $q0133 ; CHECK-NEXT: {{ $}}134 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0135 ; CHECK-NEXT: [[DUPi16_:%[0-9]+]]:fpr16 = DUPi16 [[COPY]], 1136 ; CHECK-NEXT: $h0 = COPY [[DUPi16_]]137 ; CHECK-NEXT: RET_ReallyLR implicit $h0138 %0:fpr(<8 x s16>) = COPY $q0139 %2:gpr(s64) = G_CONSTANT i64 1140 %3:fpr(s64) = COPY %2(s64)141 %1:fpr(s16) = G_EXTRACT_VECTOR_ELT %0(<8 x s16>), %3(s64)142 $h0 = COPY %1(s16)143 RET_ReallyLR implicit $h0144 145...146---147name: v8s16_fpr_zext148alignment: 4149legalized: true150regBankSelected: true151tracksRegLiveness: true152body: |153 bb.0:154 liveins: $q0155 ; CHECK-LABEL: name: v8s16_fpr_zext156 ; CHECK: liveins: $q0157 ; CHECK-NEXT: {{ $}}158 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0159 ; CHECK-NEXT: [[DUPi16_:%[0-9]+]]:fpr16 = DUPi16 [[COPY]], 1160 ; CHECK-NEXT: $h0 = COPY [[DUPi16_]]161 ; CHECK-NEXT: RET_ReallyLR implicit $h0162 %0:fpr(<8 x s16>) = COPY $q0163 %1:gpr(s32) = G_CONSTANT i32 1164 %2:gpr(s64) = G_ZEXT %1165 %3:fpr(s64) = COPY %2(s64)166 %4:fpr(s16) = G_EXTRACT_VECTOR_ELT %0(<8 x s16>), %3(s64)167 $h0 = COPY %4(s16)168 RET_ReallyLR implicit $h0169 170...171---172name: v8s16_fpr_sext173alignment: 4174legalized: true175regBankSelected: true176tracksRegLiveness: true177body: |178 bb.0:179 liveins: $q0180 ; CHECK-LABEL: name: v8s16_fpr_sext181 ; CHECK: liveins: $q0182 ; CHECK-NEXT: {{ $}}183 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0184 ; CHECK-NEXT: [[DUPi16_:%[0-9]+]]:fpr16 = DUPi16 [[COPY]], 1185 ; CHECK-NEXT: $h0 = COPY [[DUPi16_]]186 ; CHECK-NEXT: RET_ReallyLR implicit $h0187 %0:fpr(<8 x s16>) = COPY $q0188 %1:gpr(s32) = G_CONSTANT i32 1189 %2:gpr(s64) = G_SEXT %1190 %3:fpr(s64) = COPY %2(s64)191 %4:fpr(s16) = G_EXTRACT_VECTOR_ELT %0(<8 x s16>), %3(s64)192 $h0 = COPY %4(s16)193 RET_ReallyLR implicit $h0194 195...196---197name: v8s16_fpr_trunc198alignment: 4199legalized: true200regBankSelected: true201tracksRegLiveness: true202body: |203 bb.0:204 liveins: $q0205 ; CHECK-LABEL: name: v8s16_fpr_trunc206 ; CHECK: liveins: $q0207 ; CHECK-NEXT: {{ $}}208 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0209 ; CHECK-NEXT: [[DUPi16_:%[0-9]+]]:fpr16 = DUPi16 [[COPY]], 1210 ; CHECK-NEXT: $h0 = COPY [[DUPi16_]]211 ; CHECK-NEXT: RET_ReallyLR implicit $h0212 %0:fpr(<8 x s16>) = COPY $q0213 %1:gpr(s64) = G_CONSTANT i64 1214 %2:gpr(s32) = G_TRUNC %1215 %3:gpr(s64) = G_SEXT %2216 %4:fpr(s64) = COPY %3(s64)217 %5:fpr(s16) = G_EXTRACT_VECTOR_ELT %0(<8 x s16>), %4(s64)218 $h0 = COPY %5(s16)219 RET_ReallyLR implicit $h0220...221---222name: v16s8223alignment: 4224legalized: true225regBankSelected: true226tracksRegLiveness: true227liveins:228 - { reg: '$q0' }229body: |230 bb.1:231 liveins: $q0232 233 ; CHECK-LABEL: name: v16s8234 ; CHECK: liveins: $q0235 ; CHECK-NEXT: {{ $}}236 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0237 ; CHECK-NEXT: [[UMOVvi8_:%[0-9]+]]:gpr32 = UMOVvi8 [[COPY]], 0238 ; CHECK-NEXT: $w0 = COPY [[UMOVvi8_]]239 ; CHECK-NEXT: RET_ReallyLR implicit $w0240 %0:fpr(<16 x s8>) = COPY $q0241 %2:gpr(s64) = G_CONSTANT i64 0242 %1:fpr(s8) = G_EXTRACT_VECTOR_ELT %0(<16 x s8>), %2(s64)243 %4:gpr(s8) = COPY %1(s8)244 %3:gpr(s32) = G_ANYEXT %4(s8)245 $w0 = COPY %3(s32)246 RET_ReallyLR implicit $w0247 248...249---250name: v8s8251alignment: 4252legalized: true253regBankSelected: true254tracksRegLiveness: true255liveins:256 - { reg: '$q0' }257body: |258 bb.1:259 liveins: $d0260 261 ; CHECK-LABEL: name: v8s8262 ; CHECK: liveins: $d0263 ; CHECK-NEXT: {{ $}}264 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0265 ; CHECK-NEXT: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF266 ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.dsub267 ; CHECK-NEXT: [[UMOVvi8_:%[0-9]+]]:gpr32 = UMOVvi8 [[INSERT_SUBREG]], 0268 ; CHECK-NEXT: $w0 = COPY [[UMOVvi8_]]269 ; CHECK-NEXT: RET_ReallyLR implicit $w0270 %0:fpr(<8 x s8>) = COPY $d0271 %2:gpr(s64) = G_CONSTANT i64 0272 %1:fpr(s8) = G_EXTRACT_VECTOR_ELT %0(<8 x s8>), %2(s64)273 %4:gpr(s8) = COPY %1(s8)274 %3:gpr(s32) = G_ANYEXT %4(s8)275 $w0 = COPY %3(s32)276 RET_ReallyLR implicit $w0277 278...279---280name: v2p0281alignment: 4282legalized: true283regBankSelected: true284tracksRegLiveness: true285body: |286 bb.0:287 liveins: $q0288 289 ; CHECK-LABEL: name: v2p0290 ; CHECK: liveins: $q0291 ; CHECK-NEXT: {{ $}}292 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0293 ; CHECK-NEXT: [[DUPi64_:%[0-9]+]]:fpr64 = DUPi64 [[COPY]], 1294 ; CHECK-NEXT: $d0 = COPY [[DUPi64_]]295 ; CHECK-NEXT: RET_ReallyLR implicit $d0296 %0:fpr(<2 x p0>) = COPY $q0297 %2:gpr(s64) = G_CONSTANT i64 1298 %1:fpr(p0) = G_EXTRACT_VECTOR_ELT %0(<2 x p0>), %2(s64)299 $d0 = COPY %1(p0)300 RET_ReallyLR implicit $d0301 302...303