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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -verify-machineinstrs -mtriple aarch64-unknown-unknown -run-pass=instruction-select %s -o - | FileCheck %s3---4name: f64_faddp5alignment: 46legalized: true7regBankSelected: true8tracksRegLiveness: true9liveins:10 - { reg: '$q0' }11frameInfo:12 maxAlignment: 113body: |14 bb.1:15 liveins: $q016 17 ; CHECK-LABEL: name: f64_faddp18 ; CHECK: liveins: $q019 ; CHECK-NEXT: {{ $}}20 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q021 ; CHECK-NEXT: [[FADDPv2i64p:%[0-9]+]]:fpr64 = nofpexcept FADDPv2i64p [[COPY]], implicit $fpcr22 ; CHECK-NEXT: $d0 = COPY [[FADDPv2i64p]]23 ; CHECK-NEXT: RET_ReallyLR implicit $d024 %0:fpr(<2 x s64>) = COPY $q025 %6:gpr(s64) = G_CONSTANT i64 026 %7:fpr(s64) = G_EXTRACT_VECTOR_ELT %0(<2 x s64>), %6(s64)27 %8:gpr(s64) = G_CONSTANT i64 128 %9:fpr(s64) = G_EXTRACT_VECTOR_ELT %0(<2 x s64>), %8(s64)29 %4:fpr(s64) = G_FADD %7, %930 $d0 = COPY %4(s64)31 RET_ReallyLR implicit $d032 33...34---35name: f32_faddp36alignment: 437legalized: true38regBankSelected: true39tracksRegLiveness: true40liveins:41 - { reg: '$d0' }42frameInfo:43 maxAlignment: 144body: |45 bb.1:46 liveins: $d047 48 ; CHECK-LABEL: name: f32_faddp49 ; CHECK: liveins: $d050 ; CHECK-NEXT: {{ $}}51 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d052 ; CHECK-NEXT: [[FADDPv2i32p:%[0-9]+]]:fpr32 = nofpexcept FADDPv2i32p [[COPY]], implicit $fpcr53 ; CHECK-NEXT: $s0 = COPY [[FADDPv2i32p]]54 ; CHECK-NEXT: RET_ReallyLR implicit $s055 %0:fpr(<2 x s32>) = COPY $d056 %6:gpr(s64) = G_CONSTANT i64 057 %7:fpr(s32) = G_EXTRACT_VECTOR_ELT %0(<2 x s32>), %6(s64)58 %8:gpr(s64) = G_CONSTANT i64 159 %9:fpr(s32) = G_EXTRACT_VECTOR_ELT %0(<2 x s32>), %8(s64)60 %4:fpr(s32) = G_FADD %7, %961 $s0 = COPY %4(s32)62 RET_ReallyLR implicit $s063 64...65