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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -O0 -mtriple=aarch64 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s3# Verify that we get FCMPSri when we compare against 0.0 and that we get4# FCMPSrr otherwise.5 6...7---8name: zero9alignment: 410legalized: true11regBankSelected: true12tracksRegLiveness: true13body: |14 bb.1:15 liveins: $s0, $s116 17 ; CHECK-LABEL: name: zero18 ; CHECK: liveins: $s0, $s119 ; CHECK-NEXT: {{ $}}20 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $s021 ; CHECK-NEXT: nofpexcept FCMPSri [[COPY]], implicit-def $nzcv, implicit $fpcr22 ; CHECK-NEXT: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 1, implicit $nzcv23 ; CHECK-NEXT: $s0 = COPY [[CSINCWr]]24 ; CHECK-NEXT: RET_ReallyLR implicit $s025 %0:fpr(s32) = COPY $s026 %1:fpr(s32) = COPY $s127 %2:fpr(s32) = G_FCONSTANT float 0.000000e+0028 %3:gpr(s32) = G_FCMP floatpred(oeq), %0(s32), %229 $s0 = COPY %3(s32)30 RET_ReallyLR implicit $s031 32...33---34name: notzero35alignment: 436legalized: true37regBankSelected: true38tracksRegLiveness: true39machineFunctionInfo: {}40body: |41 bb.1:42 liveins: $s0, $s143 44 ; CHECK-LABEL: name: notzero45 ; CHECK: liveins: $s0, $s146 ; CHECK-NEXT: {{ $}}47 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $s048 ; CHECK-NEXT: [[FMOVSi:%[0-9]+]]:fpr32 = FMOVSi 11249 ; CHECK-NEXT: nofpexcept FCMPSrr [[COPY]], [[FMOVSi]], implicit-def $nzcv, implicit $fpcr50 ; CHECK-NEXT: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 1, implicit $nzcv51 ; CHECK-NEXT: $s0 = COPY [[CSINCWr]]52 ; CHECK-NEXT: RET_ReallyLR implicit $s053 %0:fpr(s32) = COPY $s054 %1:fpr(s32) = COPY $s155 %2:fpr(s32) = G_FCONSTANT float 1.000000e+0056 %3:gpr(s32) = G_FCMP floatpred(oeq), %0(s32), %257 $s0 = COPY %3(s32)58 RET_ReallyLR implicit $s059 60...61---62name: notzero_s6463alignment: 464legalized: true65regBankSelected: true66tracksRegLiveness: true67machineFunctionInfo: {}68body: |69 bb.1:70 liveins: $d0, $d171 72 ; CHECK-LABEL: name: notzero_s6473 ; CHECK: liveins: $d0, $d174 ; CHECK-NEXT: {{ $}}75 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d076 ; CHECK-NEXT: [[FMOVDi:%[0-9]+]]:fpr64 = FMOVDi 11277 ; CHECK-NEXT: nofpexcept FCMPDrr [[COPY]], [[FMOVDi]], implicit-def $nzcv, implicit $fpcr78 ; CHECK-NEXT: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 1, implicit $nzcv79 ; CHECK-NEXT: $s0 = COPY [[CSINCWr]]80 ; CHECK-NEXT: RET_ReallyLR implicit $s081 %0:fpr(s64) = COPY $d082 %1:fpr(s64) = COPY $d183 %2:fpr(s64) = G_FCONSTANT double 1.000000e+0084 %3:gpr(s32) = G_FCMP floatpred(oeq), %0(s64), %285 $s0 = COPY %3(s32)86 RET_ReallyLR implicit $s087 88 89...90---91name: zero_s6492alignment: 493legalized: true94regBankSelected: true95tracksRegLiveness: true96body: |97 bb.1:98 liveins: $d0, $d1, $s099 100 ; CHECK-LABEL: name: zero_s64101 ; CHECK: liveins: $d0, $d1, $s0102 ; CHECK-NEXT: {{ $}}103 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0104 ; CHECK-NEXT: nofpexcept FCMPDri [[COPY]], implicit-def $nzcv, implicit $fpcr105 ; CHECK-NEXT: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 1, implicit $nzcv106 ; CHECK-NEXT: $s0 = COPY [[CSINCWr]]107 ; CHECK-NEXT: RET_ReallyLR implicit $s0108 %0:fpr(s64) = COPY $d0109 %1:fpr(s64) = COPY $d1110 %2:fpr(s64) = G_FCONSTANT double 0.000000e+00111 %3:gpr(s32) = G_FCMP floatpred(oeq), %0(s64), %2112 $s0 = COPY %3(s32)113 RET_ReallyLR implicit $s0114...115 116---117name: zero_lhs118alignment: 4119legalized: true120regBankSelected: true121tracksRegLiveness: true122body: |123 bb.1:124 liveins: $s0, $s1125 126 ; CHECK-LABEL: name: zero_lhs127 ; CHECK: liveins: $s0, $s1128 ; CHECK-NEXT: {{ $}}129 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $s0130 ; CHECK-NEXT: nofpexcept FCMPSri [[COPY]], implicit-def $nzcv, implicit $fpcr131 ; CHECK-NEXT: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 1, implicit $nzcv132 ; CHECK-NEXT: $s0 = COPY [[CSINCWr]]133 ; CHECK-NEXT: RET_ReallyLR implicit $s0134 %0:fpr(s32) = COPY $s0135 %1:fpr(s32) = COPY $s1136 %2:fpr(s32) = G_FCONSTANT float 0.000000e+00137 %3:gpr(s32) = G_FCMP floatpred(oeq), %2(s32), %0138 $s0 = COPY %3(s32)139 RET_ReallyLR implicit $s0140 141...142---143name: zero_lhs_not_commutative_pred144alignment: 4145legalized: true146regBankSelected: true147tracksRegLiveness: true148body: |149 bb.1:150 liveins: $s0, $s1151 152 ; CHECK-LABEL: name: zero_lhs_not_commutative_pred153 ; CHECK: liveins: $s0, $s1154 ; CHECK-NEXT: {{ $}}155 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $s0156 ; CHECK-NEXT: [[FMOVS0_:%[0-9]+]]:fpr32 = FMOVS0157 ; CHECK-NEXT: nofpexcept FCMPSrr [[FMOVS0_]], [[COPY]], implicit-def $nzcv, implicit $fpcr158 ; CHECK-NEXT: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 5, implicit $nzcv159 ; CHECK-NEXT: $s0 = COPY [[CSINCWr]]160 ; CHECK-NEXT: RET_ReallyLR implicit $s0161 %0:fpr(s32) = COPY $s0162 %1:fpr(s32) = COPY $s1163 %2:fpr(s32) = G_FCONSTANT float 0.000000e+00164 %3:gpr(s32) = G_FCMP floatpred(olt), %2(s32), %0165 $s0 = COPY %3(s32)166 RET_ReallyLR implicit $s0167 168...169