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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=aarch64 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s3 4---5name: v2s32_fmul_indexed6alignment: 47legalized: true8regBankSelected: true9tracksRegLiveness: true10liveins:11 - { reg: '$d0' }12 - { reg: '$x0' }13frameInfo:14 maxAlignment: 115body: |16 bb.1:17 liveins: $d0, $x018 19 ; CHECK-LABEL: name: v2s32_fmul_indexed20 ; CHECK: liveins: $d0, $x021 ; CHECK-NEXT: {{ $}}22 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d023 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64sp = COPY $x024 ; CHECK-NEXT: [[LDRDui:%[0-9]+]]:fpr64 = LDRDui [[COPY1]], 0 :: (load (<2 x s32>), align 4)25 ; CHECK-NEXT: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF26 ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[LDRDui]], %subreg.dsub27 ; CHECK-NEXT: [[FMULv2i32_indexed:%[0-9]+]]:fpr64 = nofpexcept FMULv2i32_indexed [[COPY]], [[INSERT_SUBREG]], 0, implicit $fpcr28 ; CHECK-NEXT: $d0 = COPY [[FMULv2i32_indexed]]29 ; CHECK-NEXT: RET_ReallyLR implicit $d030 %0:fpr(<2 x s32>) = COPY $d031 %1:gpr(p0) = COPY $x032 %2:fpr(<2 x s32>) = G_LOAD %1(p0) :: (load (<2 x s32>), align 4)33 %9:fpr(<2 x s32>) = G_IMPLICIT_DEF34 %10:fpr(<4 x s32>) = G_CONCAT_VECTORS %2(<2 x s32>), %9(<2 x s32>)35 %8:gpr(s64) = G_CONSTANT i64 036 %5:fpr(<2 x s32>) = G_DUPLANE32 %10, %8(s64)37 %7:fpr(<2 x s32>) = G_FMUL %0, %538 $d0 = COPY %7(<2 x s32>)39 RET_ReallyLR implicit $d040 41...42