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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc %s -verify-machineinstrs -mtriple=aarch64-unknown-unknown -run-pass=instruction-select -mattr=+fullfp16 -o - | FileCheck %s3 4...5---6name: load_s8_s167alignment: 48legalized: true9regBankSelected: true10tracksRegLiveness: true11machineFunctionInfo: {}12body: |13 bb.0:14 liveins: $d0, $x015 ; CHECK-LABEL: name: load_s8_s1616 ; CHECK: liveins: $d0, $x017 ; CHECK-NEXT: {{ $}}18 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x019 ; CHECK-NEXT: early-clobber %3:gpr64sp, %4:fpr8 = LDRBpost [[COPY]], 4 :: (load (s8))20 ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:fpr16 = SUBREG_TO_REG 0, %4, %subreg.bsub21 ; CHECK-NEXT: $h0 = COPY [[SUBREG_TO_REG]]22 ; CHECK-NEXT: $x0 = COPY %323 ; CHECK-NEXT: RET_ReallyLR implicit $d024 %0:gpr(p0) = COPY $x025 %1:gpr(s64) = G_CONSTANT i64 426 %2:fpr(s16), %3:gpr(p0) = G_INDEXED_LOAD %0:gpr, %1:gpr, 0 :: (load (s8))27 $h0 = COPY %2(s16)28 $x0 = COPY %3(p0)29 RET_ReallyLR implicit $d030 31...32---33name: load_s8_s3234alignment: 435legalized: true36regBankSelected: true37tracksRegLiveness: true38machineFunctionInfo: {}39body: |40 bb.0:41 liveins: $d0, $x042 ; CHECK-LABEL: name: load_s8_s3243 ; CHECK: liveins: $d0, $x044 ; CHECK-NEXT: {{ $}}45 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x046 ; CHECK-NEXT: early-clobber %3:gpr64sp, %4:fpr8 = LDRBpost [[COPY]], 4 :: (load (s8))47 ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:fpr32 = SUBREG_TO_REG 0, %4, %subreg.bsub48 ; CHECK-NEXT: $s0 = COPY [[SUBREG_TO_REG]]49 ; CHECK-NEXT: $x0 = COPY %350 ; CHECK-NEXT: RET_ReallyLR implicit $d051 %0:gpr(p0) = COPY $x052 %1:gpr(s64) = G_CONSTANT i64 453 %2:fpr(s32), %3:gpr(p0) = G_INDEXED_LOAD %0:gpr, %1:gpr, 0 :: (load (s8))54 $s0 = COPY %2(s32)55 $x0 = COPY %3(p0)56 RET_ReallyLR implicit $d057 58...59---60name: load_s8_s6461alignment: 462legalized: true63regBankSelected: true64tracksRegLiveness: true65machineFunctionInfo: {}66body: |67 bb.0:68 liveins: $d0, $x069 ; CHECK-LABEL: name: load_s8_s6470 ; CHECK: liveins: $d0, $x071 ; CHECK-NEXT: {{ $}}72 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x073 ; CHECK-NEXT: early-clobber %3:gpr64sp, %4:fpr8 = LDRBpost [[COPY]], 4 :: (load (s8))74 ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:fpr64 = SUBREG_TO_REG 0, %4, %subreg.bsub75 ; CHECK-NEXT: $d0 = COPY [[SUBREG_TO_REG]]76 ; CHECK-NEXT: $x0 = COPY %377 ; CHECK-NEXT: RET_ReallyLR implicit $d078 %0:gpr(p0) = COPY $x079 %1:gpr(s64) = G_CONSTANT i64 480 %2:fpr(s64), %3:gpr(p0) = G_INDEXED_LOAD %0:gpr, %1:gpr, 0 :: (load (s8))81 $d0 = COPY %2(s64)82 $x0 = COPY %3(p0)83 RET_ReallyLR implicit $d084 85...86---87name: load_s16_s3288alignment: 489legalized: true90regBankSelected: true91tracksRegLiveness: true92machineFunctionInfo: {}93body: |94 bb.0:95 liveins: $d0, $x096 ; CHECK-LABEL: name: load_s16_s3297 ; CHECK: liveins: $d0, $x098 ; CHECK-NEXT: {{ $}}99 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0100 ; CHECK-NEXT: early-clobber %3:gpr64sp, %4:fpr16 = LDRHpost [[COPY]], 4 :: (load (s16))101 ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:fpr32 = SUBREG_TO_REG 0, %4, %subreg.hsub102 ; CHECK-NEXT: $s0 = COPY [[SUBREG_TO_REG]]103 ; CHECK-NEXT: $x0 = COPY %3104 ; CHECK-NEXT: RET_ReallyLR implicit $d0105 %0:gpr(p0) = COPY $x0106 %1:gpr(s64) = G_CONSTANT i64 4107 %2:fpr(s32), %3:gpr(p0) = G_INDEXED_LOAD %0:gpr, %1:gpr, 0 :: (load (s16))108 $s0 = COPY %2(s32)109 $x0 = COPY %3(p0)110 RET_ReallyLR implicit $d0111 112...113---114name: load_s16_s64115alignment: 4116legalized: true117regBankSelected: true118tracksRegLiveness: true119machineFunctionInfo: {}120body: |121 bb.0:122 liveins: $d0, $x0123 ; CHECK-LABEL: name: load_s16_s64124 ; CHECK: liveins: $d0, $x0125 ; CHECK-NEXT: {{ $}}126 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0127 ; CHECK-NEXT: early-clobber %3:gpr64sp, %4:fpr16 = LDRHpost [[COPY]], 4 :: (load (s16))128 ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:fpr64 = SUBREG_TO_REG 0, %4, %subreg.hsub129 ; CHECK-NEXT: $d0 = COPY [[SUBREG_TO_REG]]130 ; CHECK-NEXT: $x0 = COPY %3131 ; CHECK-NEXT: RET_ReallyLR implicit $d0132 %0:gpr(p0) = COPY $x0133 %1:gpr(s64) = G_CONSTANT i64 4134 %2:fpr(s64), %3:gpr(p0) = G_INDEXED_LOAD %0:gpr, %1:gpr, 0 :: (load (s16))135 $d0 = COPY %2(s64)136 $x0 = COPY %3(p0)137 RET_ReallyLR implicit $d0138 139...140---141name: load_s32_s64142alignment: 4143legalized: true144regBankSelected: true145tracksRegLiveness: true146machineFunctionInfo: {}147body: |148 bb.0:149 liveins: $d0, $x0150 ; CHECK-LABEL: name: load_s32_s64151 ; CHECK: liveins: $d0, $x0152 ; CHECK-NEXT: {{ $}}153 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0154 ; CHECK-NEXT: early-clobber %3:gpr64sp, %4:fpr32 = LDRSpost [[COPY]], 4 :: (load (s32))155 ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:fpr64 = SUBREG_TO_REG 0, %4, %subreg.ssub156 ; CHECK-NEXT: $d0 = COPY [[SUBREG_TO_REG]]157 ; CHECK-NEXT: $x0 = COPY %3158 ; CHECK-NEXT: RET_ReallyLR implicit $d0159 %0:gpr(p0) = COPY $x0160 %1:gpr(s64) = G_CONSTANT i64 4161 %2:fpr(s64), %3:gpr(p0) = G_INDEXED_LOAD %0:gpr, %1:gpr, 0 :: (load (s32))162 $d0 = COPY %2(s64)163 $x0 = COPY %3(p0)164 RET_ReallyLR implicit $d0165 166...167---168name: load_s8_s16_pre169alignment: 4170legalized: true171regBankSelected: true172tracksRegLiveness: true173machineFunctionInfo: {}174body: |175 bb.0:176 liveins: $d0, $x0177 ; CHECK-LABEL: name: load_s8_s16_pre178 ; CHECK: liveins: $d0, $x0179 ; CHECK-NEXT: {{ $}}180 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0181 ; CHECK-NEXT: early-clobber %3:gpr64sp, %4:fpr8 = LDRBpre [[COPY]], 4 :: (load (s8))182 ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:fpr16 = SUBREG_TO_REG 0, %4, %subreg.bsub183 ; CHECK-NEXT: $h0 = COPY [[SUBREG_TO_REG]]184 ; CHECK-NEXT: $x0 = COPY %3185 ; CHECK-NEXT: RET_ReallyLR implicit $d0186 %0:gpr(p0) = COPY $x0187 %1:gpr(s64) = G_CONSTANT i64 4188 %2:fpr(s16), %3:gpr(p0) = G_INDEXED_LOAD %0:gpr, %1:gpr, 1 :: (load (s8))189 $h0 = COPY %2(s16)190 $x0 = COPY %3(p0)191 RET_ReallyLR implicit $d0192 193...194---195name: load_s8_s32_pre196alignment: 4197legalized: true198regBankSelected: true199tracksRegLiveness: true200machineFunctionInfo: {}201body: |202 bb.0:203 liveins: $d0, $x0204 ; CHECK-LABEL: name: load_s8_s32_pre205 ; CHECK: liveins: $d0, $x0206 ; CHECK-NEXT: {{ $}}207 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0208 ; CHECK-NEXT: early-clobber %3:gpr64sp, %4:fpr8 = LDRBpre [[COPY]], 4 :: (load (s8))209 ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:fpr32 = SUBREG_TO_REG 0, %4, %subreg.bsub210 ; CHECK-NEXT: $s0 = COPY [[SUBREG_TO_REG]]211 ; CHECK-NEXT: $x0 = COPY %3212 ; CHECK-NEXT: RET_ReallyLR implicit $d0213 %0:gpr(p0) = COPY $x0214 %1:gpr(s64) = G_CONSTANT i64 4215 %2:fpr(s32), %3:gpr(p0) = G_INDEXED_LOAD %0:gpr, %1:gpr, 1 :: (load (s8))216 $s0 = COPY %2(s32)217 $x0 = COPY %3(p0)218 RET_ReallyLR implicit $d0219 220...221---222name: load_s8_s64_pre223alignment: 4224legalized: true225regBankSelected: true226tracksRegLiveness: true227machineFunctionInfo: {}228body: |229 bb.0:230 liveins: $d0, $x0231 ; CHECK-LABEL: name: load_s8_s64_pre232 ; CHECK: liveins: $d0, $x0233 ; CHECK-NEXT: {{ $}}234 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0235 ; CHECK-NEXT: early-clobber %3:gpr64sp, %4:fpr8 = LDRBpre [[COPY]], 4 :: (load (s8))236 ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:fpr64 = SUBREG_TO_REG 0, %4, %subreg.bsub237 ; CHECK-NEXT: $d0 = COPY [[SUBREG_TO_REG]]238 ; CHECK-NEXT: $x0 = COPY %3239 ; CHECK-NEXT: RET_ReallyLR implicit $d0240 %0:gpr(p0) = COPY $x0241 %1:gpr(s64) = G_CONSTANT i64 4242 %2:fpr(s64), %3:gpr(p0) = G_INDEXED_LOAD %0:gpr, %1:gpr, 1 :: (load (s8))243 $d0 = COPY %2(s64)244 $x0 = COPY %3(p0)245 RET_ReallyLR implicit $d0246 247...248---249name: load_s16_s32_pre250alignment: 4251legalized: true252regBankSelected: true253tracksRegLiveness: true254machineFunctionInfo: {}255body: |256 bb.0:257 liveins: $d0, $x0258 ; CHECK-LABEL: name: load_s16_s32_pre259 ; CHECK: liveins: $d0, $x0260 ; CHECK-NEXT: {{ $}}261 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0262 ; CHECK-NEXT: early-clobber %3:gpr64sp, %4:fpr16 = LDRHpre [[COPY]], 4 :: (load (s16))263 ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:fpr32 = SUBREG_TO_REG 0, %4, %subreg.hsub264 ; CHECK-NEXT: $s0 = COPY [[SUBREG_TO_REG]]265 ; CHECK-NEXT: $x0 = COPY %3266 ; CHECK-NEXT: RET_ReallyLR implicit $d0267 %0:gpr(p0) = COPY $x0268 %1:gpr(s64) = G_CONSTANT i64 4269 %2:fpr(s32), %3:gpr(p0) = G_INDEXED_LOAD %0:gpr, %1:gpr, 1 :: (load (s16))270 $s0 = COPY %2(s32)271 $x0 = COPY %3(p0)272 RET_ReallyLR implicit $d0273 274...275---276name: load_s16_s64_pre277alignment: 4278legalized: true279regBankSelected: true280tracksRegLiveness: true281machineFunctionInfo: {}282body: |283 bb.0:284 liveins: $d0, $x0285 ; CHECK-LABEL: name: load_s16_s64_pre286 ; CHECK: liveins: $d0, $x0287 ; CHECK-NEXT: {{ $}}288 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0289 ; CHECK-NEXT: early-clobber %3:gpr64sp, %4:fpr16 = LDRHpre [[COPY]], 4 :: (load (s16))290 ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:fpr64 = SUBREG_TO_REG 0, %4, %subreg.hsub291 ; CHECK-NEXT: $d0 = COPY [[SUBREG_TO_REG]]292 ; CHECK-NEXT: $x0 = COPY %3293 ; CHECK-NEXT: RET_ReallyLR implicit $d0294 %0:gpr(p0) = COPY $x0295 %1:gpr(s64) = G_CONSTANT i64 4296 %2:fpr(s64), %3:gpr(p0) = G_INDEXED_LOAD %0:gpr, %1:gpr, 1 :: (load (s16))297 $d0 = COPY %2(s64)298 $x0 = COPY %3(p0)299 RET_ReallyLR implicit $d0300 301...302---303name: load_s32_s64_pre304alignment: 4305legalized: true306regBankSelected: true307tracksRegLiveness: true308machineFunctionInfo: {}309body: |310 bb.0:311 liveins: $d0, $x0312 ; CHECK-LABEL: name: load_s32_s64_pre313 ; CHECK: liveins: $d0, $x0314 ; CHECK-NEXT: {{ $}}315 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0316 ; CHECK-NEXT: early-clobber %3:gpr64sp, %4:fpr32 = LDRSpre [[COPY]], 4 :: (load (s32))317 ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:fpr64 = SUBREG_TO_REG 0, %4, %subreg.ssub318 ; CHECK-NEXT: $d0 = COPY [[SUBREG_TO_REG]]319 ; CHECK-NEXT: $x0 = COPY %3320 ; CHECK-NEXT: RET_ReallyLR implicit $d0321 %0:gpr(p0) = COPY $x0322 %1:gpr(s64) = G_CONSTANT i64 4323 %2:fpr(s64), %3:gpr(p0) = G_INDEXED_LOAD %0:gpr, %1:gpr, 1 :: (load (s32))324 $d0 = COPY %2(s64)325 $x0 = COPY %3(p0)326 RET_ReallyLR implicit $d0327 328...329