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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -verify-machineinstrs -mtriple aarch64-unknown-unknown -run-pass=instruction-select -mattr=-fullfp16 -global-isel %s -o - | FileCheck %s3 4...5---6name: test_f16.rint7alignment: 48legalized: true9regBankSelected: true10tracksRegLiveness: true11machineFunctionInfo: {}12body: |13 bb.0:14 liveins: $h015 16 ; CHECK-LABEL: name: test_f16.rint17 ; CHECK: liveins: $h018 ; CHECK-NEXT: {{ $}}19 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr16 = COPY $h020 ; CHECK-NEXT: [[FCVTSHr:%[0-9]+]]:fpr32 = nofpexcept FCVTSHr [[COPY]], implicit $fpcr21 ; CHECK-NEXT: [[FRINTXSr:%[0-9]+]]:fpr32 = nofpexcept FRINTXSr [[FCVTSHr]], implicit $fpcr22 ; CHECK-NEXT: [[FCVTHSr:%[0-9]+]]:fpr16 = nofpexcept FCVTHSr [[FRINTXSr]], implicit $fpcr23 ; CHECK-NEXT: $h0 = COPY [[FCVTHSr]]24 ; CHECK-NEXT: RET_ReallyLR implicit $h025 %0:fpr(s16) = COPY $h026 %2:fpr(s32) = G_FPEXT %0(s16)27 %3:fpr(s32) = G_FRINT %228 %1:fpr(s16) = G_FPTRUNC %3(s32)29 $h0 = COPY %1(s16)30 RET_ReallyLR implicit $h031 32...33---34name: test_v4f16.rint35alignment: 436legalized: true37regBankSelected: true38tracksRegLiveness: true39machineFunctionInfo: {}40body: |41 bb.0:42 liveins: $d043 44 ; CHECK-LABEL: name: test_v4f16.rint45 ; CHECK: liveins: $d046 ; CHECK-NEXT: {{ $}}47 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d048 ; CHECK-NEXT: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF49 ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.dsub50 ; CHECK-NEXT: [[DEF1:%[0-9]+]]:fpr128 = IMPLICIT_DEF51 ; CHECK-NEXT: [[INSERT_SUBREG1:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF1]], [[COPY]], %subreg.dsub52 ; CHECK-NEXT: [[DEF2:%[0-9]+]]:fpr128 = IMPLICIT_DEF53 ; CHECK-NEXT: [[INSERT_SUBREG2:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF2]], [[COPY]], %subreg.dsub54 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr16 = COPY [[INSERT_SUBREG]].hsub55 ; CHECK-NEXT: [[DUPi16_:%[0-9]+]]:fpr16 = DUPi16 [[INSERT_SUBREG]], 156 ; CHECK-NEXT: [[DUPi16_1:%[0-9]+]]:fpr16 = DUPi16 [[INSERT_SUBREG1]], 257 ; CHECK-NEXT: [[DUPi16_2:%[0-9]+]]:fpr16 = DUPi16 [[INSERT_SUBREG2]], 358 ; CHECK-NEXT: [[FCVTSHr:%[0-9]+]]:fpr32 = nofpexcept FCVTSHr [[COPY1]], implicit $fpcr59 ; CHECK-NEXT: [[FRINTXSr:%[0-9]+]]:fpr32 = nofpexcept FRINTXSr [[FCVTSHr]], implicit $fpcr60 ; CHECK-NEXT: [[FCVTHSr:%[0-9]+]]:fpr16 = nofpexcept FCVTHSr [[FRINTXSr]], implicit $fpcr61 ; CHECK-NEXT: [[FCVTSHr1:%[0-9]+]]:fpr32 = nofpexcept FCVTSHr [[DUPi16_]], implicit $fpcr62 ; CHECK-NEXT: [[FRINTXSr1:%[0-9]+]]:fpr32 = nofpexcept FRINTXSr [[FCVTSHr1]], implicit $fpcr63 ; CHECK-NEXT: [[FCVTHSr1:%[0-9]+]]:fpr16 = nofpexcept FCVTHSr [[FRINTXSr1]], implicit $fpcr64 ; CHECK-NEXT: [[FCVTSHr2:%[0-9]+]]:fpr32 = nofpexcept FCVTSHr [[DUPi16_1]], implicit $fpcr65 ; CHECK-NEXT: [[FRINTXSr2:%[0-9]+]]:fpr32 = nofpexcept FRINTXSr [[FCVTSHr2]], implicit $fpcr66 ; CHECK-NEXT: [[FCVTHSr2:%[0-9]+]]:fpr16 = nofpexcept FCVTHSr [[FRINTXSr2]], implicit $fpcr67 ; CHECK-NEXT: [[FCVTSHr3:%[0-9]+]]:fpr32 = nofpexcept FCVTSHr [[DUPi16_2]], implicit $fpcr68 ; CHECK-NEXT: [[FRINTXSr3:%[0-9]+]]:fpr32 = nofpexcept FRINTXSr [[FCVTSHr3]], implicit $fpcr69 ; CHECK-NEXT: [[FCVTHSr3:%[0-9]+]]:fpr16 = nofpexcept FCVTHSr [[FRINTXSr3]], implicit $fpcr70 ; CHECK-NEXT: [[DEF3:%[0-9]+]]:fpr128 = IMPLICIT_DEF71 ; CHECK-NEXT: [[INSERT_SUBREG3:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF3]], [[FCVTHSr]], %subreg.hsub72 ; CHECK-NEXT: [[DEF4:%[0-9]+]]:fpr128 = IMPLICIT_DEF73 ; CHECK-NEXT: [[INSERT_SUBREG4:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF4]], [[FCVTHSr1]], %subreg.hsub74 ; CHECK-NEXT: [[INSvi16lane:%[0-9]+]]:fpr128 = INSvi16lane [[INSERT_SUBREG3]], 1, [[INSERT_SUBREG4]], 075 ; CHECK-NEXT: [[DEF5:%[0-9]+]]:fpr128 = IMPLICIT_DEF76 ; CHECK-NEXT: [[INSERT_SUBREG5:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF5]], [[FCVTHSr2]], %subreg.hsub77 ; CHECK-NEXT: [[INSvi16lane1:%[0-9]+]]:fpr128 = INSvi16lane [[INSvi16lane]], 2, [[INSERT_SUBREG5]], 078 ; CHECK-NEXT: [[DEF6:%[0-9]+]]:fpr128 = IMPLICIT_DEF79 ; CHECK-NEXT: [[INSERT_SUBREG6:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF6]], [[FCVTHSr3]], %subreg.hsub80 ; CHECK-NEXT: [[INSvi16lane2:%[0-9]+]]:fpr128 = INSvi16lane [[INSvi16lane1]], 3, [[INSERT_SUBREG6]], 081 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr64 = COPY [[INSvi16lane2]].dsub82 ; CHECK-NEXT: $d0 = COPY [[COPY2]]83 ; CHECK-NEXT: RET_ReallyLR implicit $d084 %0:fpr(<4 x s16>) = COPY $d085 %2:fpr(s16), %3:fpr(s16), %4:fpr(s16), %5:fpr(s16) = G_UNMERGE_VALUES %0(<4 x s16>)86 %16:fpr(s32) = G_FPEXT %2(s16)87 %17:fpr(s32) = G_FRINT %1688 %6:fpr(s16) = G_FPTRUNC %17(s32)89 %14:fpr(s32) = G_FPEXT %3(s16)90 %15:fpr(s32) = G_FRINT %1491 %7:fpr(s16) = G_FPTRUNC %15(s32)92 %12:fpr(s32) = G_FPEXT %4(s16)93 %13:fpr(s32) = G_FRINT %1294 %8:fpr(s16) = G_FPTRUNC %13(s32)95 %10:fpr(s32) = G_FPEXT %5(s16)96 %11:fpr(s32) = G_FRINT %1097 %9:fpr(s16) = G_FPTRUNC %11(s32)98 %1:fpr(<4 x s16>) = G_BUILD_VECTOR %6(s16), %7(s16), %8(s16), %9(s16)99 $d0 = COPY %1(<4 x s16>)100 RET_ReallyLR implicit $d0101 102...103---104name: test_v8f16.rint105alignment: 4106legalized: true107regBankSelected: true108tracksRegLiveness: true109machineFunctionInfo: {}110body: |111 bb.0:112 liveins: $q0113 114 ; CHECK-LABEL: name: test_v8f16.rint115 ; CHECK: liveins: $q0116 ; CHECK-NEXT: {{ $}}117 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0118 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr16 = COPY [[COPY]].hsub119 ; CHECK-NEXT: [[DUPi16_:%[0-9]+]]:fpr16 = DUPi16 [[COPY]], 1120 ; CHECK-NEXT: [[DUPi16_1:%[0-9]+]]:fpr16 = DUPi16 [[COPY]], 2121 ; CHECK-NEXT: [[DUPi16_2:%[0-9]+]]:fpr16 = DUPi16 [[COPY]], 3122 ; CHECK-NEXT: [[DUPi16_3:%[0-9]+]]:fpr16 = DUPi16 [[COPY]], 4123 ; CHECK-NEXT: [[DUPi16_4:%[0-9]+]]:fpr16 = DUPi16 [[COPY]], 5124 ; CHECK-NEXT: [[DUPi16_5:%[0-9]+]]:fpr16 = DUPi16 [[COPY]], 6125 ; CHECK-NEXT: [[DUPi16_6:%[0-9]+]]:fpr16 = DUPi16 [[COPY]], 7126 ; CHECK-NEXT: [[FCVTSHr:%[0-9]+]]:fpr32 = nofpexcept FCVTSHr [[COPY1]], implicit $fpcr127 ; CHECK-NEXT: [[FRINTXSr:%[0-9]+]]:fpr32 = nofpexcept FRINTXSr [[FCVTSHr]], implicit $fpcr128 ; CHECK-NEXT: [[FCVTHSr:%[0-9]+]]:fpr16 = nofpexcept FCVTHSr [[FRINTXSr]], implicit $fpcr129 ; CHECK-NEXT: [[FCVTSHr1:%[0-9]+]]:fpr32 = nofpexcept FCVTSHr [[DUPi16_]], implicit $fpcr130 ; CHECK-NEXT: [[FRINTXSr1:%[0-9]+]]:fpr32 = nofpexcept FRINTXSr [[FCVTSHr1]], implicit $fpcr131 ; CHECK-NEXT: [[FCVTHSr1:%[0-9]+]]:fpr16 = nofpexcept FCVTHSr [[FRINTXSr1]], implicit $fpcr132 ; CHECK-NEXT: [[FCVTSHr2:%[0-9]+]]:fpr32 = nofpexcept FCVTSHr [[DUPi16_1]], implicit $fpcr133 ; CHECK-NEXT: [[FRINTXSr2:%[0-9]+]]:fpr32 = nofpexcept FRINTXSr [[FCVTSHr2]], implicit $fpcr134 ; CHECK-NEXT: [[FCVTHSr2:%[0-9]+]]:fpr16 = nofpexcept FCVTHSr [[FRINTXSr2]], implicit $fpcr135 ; CHECK-NEXT: [[FCVTSHr3:%[0-9]+]]:fpr32 = nofpexcept FCVTSHr [[DUPi16_2]], implicit $fpcr136 ; CHECK-NEXT: [[FRINTXSr3:%[0-9]+]]:fpr32 = nofpexcept FRINTXSr [[FCVTSHr3]], implicit $fpcr137 ; CHECK-NEXT: [[FCVTHSr3:%[0-9]+]]:fpr16 = nofpexcept FCVTHSr [[FRINTXSr3]], implicit $fpcr138 ; CHECK-NEXT: [[FCVTSHr4:%[0-9]+]]:fpr32 = nofpexcept FCVTSHr [[DUPi16_3]], implicit $fpcr139 ; CHECK-NEXT: [[FRINTXSr4:%[0-9]+]]:fpr32 = nofpexcept FRINTXSr [[FCVTSHr4]], implicit $fpcr140 ; CHECK-NEXT: [[FCVTHSr4:%[0-9]+]]:fpr16 = nofpexcept FCVTHSr [[FRINTXSr4]], implicit $fpcr141 ; CHECK-NEXT: [[FCVTSHr5:%[0-9]+]]:fpr32 = nofpexcept FCVTSHr [[DUPi16_4]], implicit $fpcr142 ; CHECK-NEXT: [[FRINTXSr5:%[0-9]+]]:fpr32 = nofpexcept FRINTXSr [[FCVTSHr5]], implicit $fpcr143 ; CHECK-NEXT: [[FCVTHSr5:%[0-9]+]]:fpr16 = nofpexcept FCVTHSr [[FRINTXSr5]], implicit $fpcr144 ; CHECK-NEXT: [[FCVTSHr6:%[0-9]+]]:fpr32 = nofpexcept FCVTSHr [[DUPi16_5]], implicit $fpcr145 ; CHECK-NEXT: [[FRINTXSr6:%[0-9]+]]:fpr32 = nofpexcept FRINTXSr [[FCVTSHr6]], implicit $fpcr146 ; CHECK-NEXT: [[FCVTHSr6:%[0-9]+]]:fpr16 = nofpexcept FCVTHSr [[FRINTXSr6]], implicit $fpcr147 ; CHECK-NEXT: [[FCVTSHr7:%[0-9]+]]:fpr32 = nofpexcept FCVTSHr [[DUPi16_6]], implicit $fpcr148 ; CHECK-NEXT: [[FRINTXSr7:%[0-9]+]]:fpr32 = nofpexcept FRINTXSr [[FCVTSHr7]], implicit $fpcr149 ; CHECK-NEXT: [[FCVTHSr7:%[0-9]+]]:fpr16 = nofpexcept FCVTHSr [[FRINTXSr7]], implicit $fpcr150 ; CHECK-NEXT: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF151 ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[FCVTHSr]], %subreg.hsub152 ; CHECK-NEXT: [[DEF1:%[0-9]+]]:fpr128 = IMPLICIT_DEF153 ; CHECK-NEXT: [[INSERT_SUBREG1:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF1]], [[FCVTHSr1]], %subreg.hsub154 ; CHECK-NEXT: [[INSvi16lane:%[0-9]+]]:fpr128 = INSvi16lane [[INSERT_SUBREG]], 1, [[INSERT_SUBREG1]], 0155 ; CHECK-NEXT: [[DEF2:%[0-9]+]]:fpr128 = IMPLICIT_DEF156 ; CHECK-NEXT: [[INSERT_SUBREG2:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF2]], [[FCVTHSr2]], %subreg.hsub157 ; CHECK-NEXT: [[INSvi16lane1:%[0-9]+]]:fpr128 = INSvi16lane [[INSvi16lane]], 2, [[INSERT_SUBREG2]], 0158 ; CHECK-NEXT: [[DEF3:%[0-9]+]]:fpr128 = IMPLICIT_DEF159 ; CHECK-NEXT: [[INSERT_SUBREG3:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF3]], [[FCVTHSr3]], %subreg.hsub160 ; CHECK-NEXT: [[INSvi16lane2:%[0-9]+]]:fpr128 = INSvi16lane [[INSvi16lane1]], 3, [[INSERT_SUBREG3]], 0161 ; CHECK-NEXT: [[DEF4:%[0-9]+]]:fpr128 = IMPLICIT_DEF162 ; CHECK-NEXT: [[INSERT_SUBREG4:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF4]], [[FCVTHSr4]], %subreg.hsub163 ; CHECK-NEXT: [[INSvi16lane3:%[0-9]+]]:fpr128 = INSvi16lane [[INSvi16lane2]], 4, [[INSERT_SUBREG4]], 0164 ; CHECK-NEXT: [[DEF5:%[0-9]+]]:fpr128 = IMPLICIT_DEF165 ; CHECK-NEXT: [[INSERT_SUBREG5:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF5]], [[FCVTHSr5]], %subreg.hsub166 ; CHECK-NEXT: [[INSvi16lane4:%[0-9]+]]:fpr128 = INSvi16lane [[INSvi16lane3]], 5, [[INSERT_SUBREG5]], 0167 ; CHECK-NEXT: [[DEF6:%[0-9]+]]:fpr128 = IMPLICIT_DEF168 ; CHECK-NEXT: [[INSERT_SUBREG6:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF6]], [[FCVTHSr6]], %subreg.hsub169 ; CHECK-NEXT: [[INSvi16lane5:%[0-9]+]]:fpr128 = INSvi16lane [[INSvi16lane4]], 6, [[INSERT_SUBREG6]], 0170 ; CHECK-NEXT: [[DEF7:%[0-9]+]]:fpr128 = IMPLICIT_DEF171 ; CHECK-NEXT: [[INSERT_SUBREG7:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF7]], [[FCVTHSr7]], %subreg.hsub172 ; CHECK-NEXT: [[INSvi16lane6:%[0-9]+]]:fpr128 = INSvi16lane [[INSvi16lane5]], 7, [[INSERT_SUBREG7]], 0173 ; CHECK-NEXT: $q0 = COPY [[INSvi16lane6]]174 ; CHECK-NEXT: RET_ReallyLR implicit $q0175 %0:fpr(<8 x s16>) = COPY $q0176 %2:fpr(s16), %3:fpr(s16), %4:fpr(s16), %5:fpr(s16), %6:fpr(s16), %7:fpr(s16), %8:fpr(s16), %9:fpr(s16) = G_UNMERGE_VALUES %0(<8 x s16>)177 %32:fpr(s32) = G_FPEXT %2(s16)178 %33:fpr(s32) = G_FRINT %32179 %10:fpr(s16) = G_FPTRUNC %33(s32)180 %30:fpr(s32) = G_FPEXT %3(s16)181 %31:fpr(s32) = G_FRINT %30182 %11:fpr(s16) = G_FPTRUNC %31(s32)183 %28:fpr(s32) = G_FPEXT %4(s16)184 %29:fpr(s32) = G_FRINT %28185 %12:fpr(s16) = G_FPTRUNC %29(s32)186 %26:fpr(s32) = G_FPEXT %5(s16)187 %27:fpr(s32) = G_FRINT %26188 %13:fpr(s16) = G_FPTRUNC %27(s32)189 %24:fpr(s32) = G_FPEXT %6(s16)190 %25:fpr(s32) = G_FRINT %24191 %14:fpr(s16) = G_FPTRUNC %25(s32)192 %22:fpr(s32) = G_FPEXT %7(s16)193 %23:fpr(s32) = G_FRINT %22194 %15:fpr(s16) = G_FPTRUNC %23(s32)195 %20:fpr(s32) = G_FPEXT %8(s16)196 %21:fpr(s32) = G_FRINT %20197 %16:fpr(s16) = G_FPTRUNC %21(s32)198 %18:fpr(s32) = G_FPEXT %9(s16)199 %19:fpr(s32) = G_FRINT %18200 %17:fpr(s16) = G_FPTRUNC %19(s32)201 %1:fpr(<8 x s16>) = G_BUILD_VECTOR %10(s16), %11(s16), %12(s16), %13(s16), %14(s16), %15(s16), %16(s16), %17(s16)202 $q0 = COPY %1(<8 x s16>)203 RET_ReallyLR implicit $q0204