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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple aarch64 -debugify-and-strip-all-safe -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s3 4# Check that we remove hints during selection.5 6...7---8name: assert_zext_gpr9legalized: true10regBankSelected: true11tracksRegLiveness: true12body: |13 bb.0:14 liveins: $w0, $w115 16 ; CHECK-LABEL: name: assert_zext_gpr17 ; CHECK: liveins: $w0, $w118 ; CHECK-NEXT: {{ $}}19 ; CHECK-NEXT: %copy:gpr32 = COPY $w020 ; CHECK-NEXT: $w1 = COPY %copy21 ; CHECK-NEXT: RET_ReallyLR implicit $w122 %copy:gpr(s32) = COPY $w023 %copy_assert_zext:gpr(s32) = G_ASSERT_ZEXT %copy, 1624 $w1 = COPY %copy_assert_zext(s32)25 RET_ReallyLR implicit $w126 27...28---29name: assert_zext_fpr30legalized: true31regBankSelected: true32tracksRegLiveness: true33body: |34 bb.0:35 liveins: $s0, $s136 37 ; CHECK-LABEL: name: assert_zext_fpr38 ; CHECK: liveins: $s0, $s139 ; CHECK-NEXT: {{ $}}40 ; CHECK-NEXT: %copy:fpr32 = COPY $s041 ; CHECK-NEXT: $s1 = COPY %copy42 ; CHECK-NEXT: RET_ReallyLR implicit $s143 %copy:fpr(s32) = COPY $s044 %copy_assert_zext:fpr(s32) = G_ASSERT_ZEXT %copy, 1645 $s1 = COPY %copy_assert_zext(s32)46 RET_ReallyLR implicit $s147 48...49---50name: assert_zext_in_between_cross_bank51legalized: true52regBankSelected: true53tracksRegLiveness: true54body: |55 bb.0:56 liveins: $s0, $w157 58 ; CHECK-LABEL: name: assert_zext_in_between_cross_bank59 ; CHECK: liveins: $s0, $w160 ; CHECK-NEXT: {{ $}}61 ; CHECK-NEXT: %copy:fpr32 = COPY $s062 ; CHECK-NEXT: $w1 = COPY %copy63 ; CHECK-NEXT: RET_ReallyLR implicit $w164 %copy:fpr(s32) = COPY $s065 %copy_assert_zext:fpr(s32) = G_ASSERT_ZEXT %copy, 1666 $w1 = COPY %copy_assert_zext(s32)67 RET_ReallyLR implicit $w168 69...70---71name: assert_zext_decided_dst_class72legalized: true73regBankSelected: true74tracksRegLiveness: true75body: |76 bb.0:77 liveins: $w0, $w1, $w278 79 ; Users of G_ASSERT_ZEXT may end up deciding the destination register class.80 ; Make sure that the source register class is constrained.81 82 ; CHECK-LABEL: name: assert_zext_decided_dst_class83 ; CHECK: liveins: $w0, $w1, $w284 ; CHECK-NEXT: {{ $}}85 ; CHECK-NEXT: %copy_with_rc:gpr32sp = COPY $w286 ; CHECK-NEXT: $w1 = COPY %copy_with_rc87 ; CHECK-NEXT: RET_ReallyLR implicit $w188 %copy:gpr(s32) = COPY $w089 %copy_assert_zext:gpr(s32) = G_ASSERT_ZEXT %copy, 1690 %copy_with_rc:gpr32sp(s32) = COPY $w291 $w1 = COPY %copy_with_rc(s32)92 RET_ReallyLR implicit $w193 94...95---96name: assert_sext_gpr97legalized: true98regBankSelected: true99tracksRegLiveness: true100body: |101 bb.0:102 liveins: $w0, $w1103 104 ; CHECK-LABEL: name: assert_sext_gpr105 ; CHECK: liveins: $w0, $w1106 ; CHECK-NEXT: {{ $}}107 ; CHECK-NEXT: %copy:gpr32 = COPY $w0108 ; CHECK-NEXT: $w1 = COPY %copy109 ; CHECK-NEXT: RET_ReallyLR implicit $w1110 %copy:gpr(s32) = COPY $w0111 %copy_assert_sext:gpr(s32) = G_ASSERT_SEXT %copy, 16112 $w1 = COPY %copy_assert_sext(s32)113 RET_ReallyLR implicit $w1114 115...116---117name: assert_sext_fpr118legalized: true119regBankSelected: true120tracksRegLiveness: true121body: |122 bb.0:123 liveins: $s0, $s1124 125 ; CHECK-LABEL: name: assert_sext_fpr126 ; CHECK: liveins: $s0, $s1127 ; CHECK-NEXT: {{ $}}128 ; CHECK-NEXT: %copy:fpr32 = COPY $s0129 ; CHECK-NEXT: $s1 = COPY %copy130 ; CHECK-NEXT: RET_ReallyLR implicit $s1131 %copy:fpr(s32) = COPY $s0132 %copy_assert_sext:fpr(s32) = G_ASSERT_SEXT %copy, 16133 $s1 = COPY %copy_assert_sext(s32)134 RET_ReallyLR implicit $s1135 136...137---138name: assert_sext_in_between_cross_bank139legalized: true140regBankSelected: true141tracksRegLiveness: true142body: |143 bb.0:144 liveins: $s0, $w1145 146 ; CHECK-LABEL: name: assert_sext_in_between_cross_bank147 ; CHECK: liveins: $s0, $w1148 ; CHECK-NEXT: {{ $}}149 ; CHECK-NEXT: %copy:fpr32 = COPY $s0150 ; CHECK-NEXT: $w1 = COPY %copy151 ; CHECK-NEXT: RET_ReallyLR implicit $w1152 %copy:fpr(s32) = COPY $s0153 %copy_assert_sext:fpr(s32) = G_ASSERT_SEXT %copy, 16154 $w1 = COPY %copy_assert_sext(s32)155 RET_ReallyLR implicit $w1156 157...158---159name: assert_sext_decided_dst_class160legalized: true161regBankSelected: true162tracksRegLiveness: true163body: |164 bb.0:165 liveins: $w0, $w1, $w2166 167 ; Users of G_ASSERT_SEXT may end up deciding the destination register class.168 ; Make sure that the source register class is constrained.169 170 ; CHECK-LABEL: name: assert_sext_decided_dst_class171 ; CHECK: liveins: $w0, $w1, $w2172 ; CHECK-NEXT: {{ $}}173 ; CHECK-NEXT: %copy_with_rc:gpr32sp = COPY $w2174 ; CHECK-NEXT: $w1 = COPY %copy_with_rc175 ; CHECK-NEXT: RET_ReallyLR implicit $w1176 %copy:gpr(s32) = COPY $w0177 %copy_assert_sext:gpr(s32) = G_ASSERT_SEXT %copy, 16178 %copy_with_rc:gpr32sp(s32) = COPY $w2179 $w1 = COPY %copy_with_rc(s32)180 RET_ReallyLR implicit $w1181