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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -O0 -mtriple=aarch64-- -run-pass=instruction-select -global-isel-abort=1 -verify-machineinstrs %s -o - | FileCheck %s3# RUN: llc -O0 -mtriple=aarch64-- -run-pass=instruction-select -global-isel-abort=1 --code-model=tiny -verify-machineinstrs %s -o - | FileCheck -check-prefix=CHECK-TINY %s4 5--- |6 target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"7 8 define void @imm_s32_gpr() { ret void }9 define void @imm_s64_gpr() { ret void }10 define void @test_f64_cp() { ret void }11 define void @test_f32_cp_optsize() #0 { ret void }12 define void @test_f32_cp_minsize() #1 { ret void }13 14 15 attributes #0 = { optsize }16 attributes #1 = { minsize }17 18...19 20---21# Check that we select a 32-bit immediate into a MOVi32imm.22name: imm_s32_gpr23legalized: true24regBankSelected: true25 26registers:27 - { id: 0, class: gpr }28 29body: |30 bb.0:31 liveins: $w0, $w132 33 ; CHECK-LABEL: name: imm_s32_gpr34 ; CHECK: liveins: $w0, $w135 ; CHECK-NEXT: {{ $}}36 ; CHECK-NEXT: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm -123437 ; CHECK-NEXT: $w0 = COPY [[MOVi32imm]]38 ;39 ; CHECK-TINY-LABEL: name: imm_s32_gpr40 ; CHECK-TINY: liveins: $w0, $w141 ; CHECK-TINY-NEXT: {{ $}}42 ; CHECK-TINY-NEXT: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm -123443 ; CHECK-TINY-NEXT: $w0 = COPY [[MOVi32imm]]44 %0(s32) = G_CONSTANT i32 -123445 $w0 = COPY %0(s32)46...47 48---49# Check that we select a 64-bit immediate into a MOVi64imm.50name: imm_s64_gpr51legalized: true52regBankSelected: true53 54registers:55 - { id: 0, class: gpr }56 57body: |58 bb.0:59 liveins: $w0, $w160 61 ; CHECK-LABEL: name: imm_s64_gpr62 ; CHECK: liveins: $w0, $w163 ; CHECK-NEXT: {{ $}}64 ; CHECK-NEXT: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 123465 ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64all = SUBREG_TO_REG 0, [[MOVi32imm]], %subreg.sub_3266 ; CHECK-NEXT: $x0 = COPY [[SUBREG_TO_REG]]67 ;68 ; CHECK-TINY-LABEL: name: imm_s64_gpr69 ; CHECK-TINY: liveins: $w0, $w170 ; CHECK-TINY-NEXT: {{ $}}71 ; CHECK-TINY-NEXT: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 123472 ; CHECK-TINY-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64all = SUBREG_TO_REG 0, [[MOVi32imm]], %subreg.sub_3273 ; CHECK-TINY-NEXT: $x0 = COPY [[SUBREG_TO_REG]]74 %0(s64) = G_CONSTANT i64 123475 $x0 = COPY %0(s64)76...77 78# 64b FP immediates need to be loaded.79---80name: test_f64_cp81legalized: true82regBankSelected: true83liveins:84 - { reg: '$d0' }85body: |86 bb.1 (%ir-block.0):87 liveins: $d088 89 ; CHECK-LABEL: name: test_f64_cp90 ; CHECK: liveins: $d091 ; CHECK-NEXT: {{ $}}92 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d093 ; CHECK-NEXT: [[ADRP:%[0-9]+]]:gpr64common = ADRP target-flags(aarch64-page) %const.094 ; CHECK-NEXT: [[LDRDui:%[0-9]+]]:fpr64 = LDRDui [[ADRP]], target-flags(aarch64-pageoff, aarch64-nc) %const.0 :: (load (s64) from constant-pool)95 ; CHECK-NEXT: [[FADDDrr:%[0-9]+]]:fpr64 = nofpexcept FADDDrr [[COPY]], [[LDRDui]], implicit $fpcr96 ; CHECK-NEXT: $d0 = COPY [[FADDDrr]]97 ; CHECK-NEXT: RET_ReallyLR implicit $d098 ;99 ; CHECK-TINY-LABEL: name: test_f64_cp100 ; CHECK-TINY: liveins: $d0101 ; CHECK-TINY-NEXT: {{ $}}102 ; CHECK-TINY-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0103 ; CHECK-TINY-NEXT: [[LDRDl:%[0-9]+]]:fpr64 = LDRDl %const.0 :: (load (s64) from constant-pool)104 ; CHECK-TINY-NEXT: [[FADDDrr:%[0-9]+]]:fpr64 = nofpexcept FADDDrr [[COPY]], [[LDRDl]], implicit $fpcr105 ; CHECK-TINY-NEXT: $d0 = COPY [[FADDDrr]]106 ; CHECK-TINY-NEXT: RET_ReallyLR implicit $d0107 %0:fpr(s64) = COPY $d0108 %1:fpr(s64) = G_FCONSTANT double 0x3FEFF7CED916872B109 %2:fpr(s64) = G_FADD %0, %1110 $d0 = COPY %2(s64)111 RET_ReallyLR implicit $d0112 113...114# 32b FP immediates need to be loaded if using optsize.115---116name: test_f32_cp_optsize117legalized: true118regBankSelected: true119liveins:120 - { reg: '$s0' }121body: |122 bb.1 (%ir-block.0):123 liveins: $s0124 125 ; CHECK-LABEL: name: test_f32_cp_optsize126 ; CHECK: liveins: $s0127 ; CHECK-NEXT: {{ $}}128 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $s0129 ; CHECK-NEXT: [[ADRP:%[0-9]+]]:gpr64common = ADRP target-flags(aarch64-page) %const.0130 ; CHECK-NEXT: [[LDRSui:%[0-9]+]]:fpr32 = LDRSui [[ADRP]], target-flags(aarch64-pageoff, aarch64-nc) %const.0 :: (load (s32) from constant-pool)131 ; CHECK-NEXT: [[FADDSrr:%[0-9]+]]:fpr32 = nofpexcept FADDSrr [[COPY]], [[LDRSui]], implicit $fpcr132 ; CHECK-NEXT: $s0 = COPY [[FADDSrr]]133 ; CHECK-NEXT: RET_ReallyLR implicit $s0134 ;135 ; CHECK-TINY-LABEL: name: test_f32_cp_optsize136 ; CHECK-TINY: liveins: $s0137 ; CHECK-TINY-NEXT: {{ $}}138 ; CHECK-TINY-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $s0139 ; CHECK-TINY-NEXT: [[LDRSl:%[0-9]+]]:fpr32 = LDRSl %const.0 :: (load (s32) from constant-pool)140 ; CHECK-TINY-NEXT: [[FADDSrr:%[0-9]+]]:fpr32 = nofpexcept FADDSrr [[COPY]], [[LDRSl]], implicit $fpcr141 ; CHECK-TINY-NEXT: $s0 = COPY [[FADDSrr]]142 ; CHECK-TINY-NEXT: RET_ReallyLR implicit $s0143 %0:fpr(s32) = COPY $s0144 %1:fpr(s32) = G_FCONSTANT float 0x3FDB267DE0000000145 %2:fpr(s32) = G_FADD %0, %1146 $s0 = COPY %2(s32)147 RET_ReallyLR implicit $s0148 149...150# 32b FP immediates need to be loaded if using minsize.151---152name: test_f32_cp_minsize153legalized: true154regBankSelected: true155liveins:156 - { reg: '$s0' }157body: |158 bb.1 (%ir-block.0):159 liveins: $s0160 161 ; CHECK-LABEL: name: test_f32_cp_minsize162 ; CHECK: liveins: $s0163 ; CHECK-NEXT: {{ $}}164 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $s0165 ; CHECK-NEXT: [[ADRP:%[0-9]+]]:gpr64common = ADRP target-flags(aarch64-page) %const.0166 ; CHECK-NEXT: [[LDRSui:%[0-9]+]]:fpr32 = LDRSui [[ADRP]], target-flags(aarch64-pageoff, aarch64-nc) %const.0 :: (load (s32) from constant-pool)167 ; CHECK-NEXT: [[FADDSrr:%[0-9]+]]:fpr32 = nofpexcept FADDSrr [[COPY]], [[LDRSui]], implicit $fpcr168 ; CHECK-NEXT: $s0 = COPY [[FADDSrr]]169 ; CHECK-NEXT: RET_ReallyLR implicit $s0170 ;171 ; CHECK-TINY-LABEL: name: test_f32_cp_minsize172 ; CHECK-TINY: liveins: $s0173 ; CHECK-TINY-NEXT: {{ $}}174 ; CHECK-TINY-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $s0175 ; CHECK-TINY-NEXT: [[LDRSl:%[0-9]+]]:fpr32 = LDRSl %const.0 :: (load (s32) from constant-pool)176 ; CHECK-TINY-NEXT: [[FADDSrr:%[0-9]+]]:fpr32 = nofpexcept FADDSrr [[COPY]], [[LDRSl]], implicit $fpcr177 ; CHECK-TINY-NEXT: $s0 = COPY [[FADDSrr]]178 ; CHECK-TINY-NEXT: RET_ReallyLR implicit $s0179 %0:fpr(s32) = COPY $s0180 %1:fpr(s32) = G_FCONSTANT float 0x3FDB267DE0000000181 %2:fpr(s32) = G_FADD %0, %1182 $s0 = COPY %2(s32)183 RET_ReallyLR implicit $s0184 185...186