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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -verify-machineinstrs -mtriple aarch64-unknown-unknown -run-pass=instruction-select %s -o - | FileCheck %s3---4name: v16s8_gpr5alignment: 46legalized: true7regBankSelected: true8tracksRegLiveness: true9body: |10 bb.0:11 liveins: $q1, $w012 13 ; CHECK-LABEL: name: v16s8_gpr14 ; CHECK: liveins: $q1, $w015 ; CHECK-NEXT: {{ $}}16 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w017 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q118 ; CHECK-NEXT: [[INSvi8gpr:%[0-9]+]]:fpr128 = INSvi8gpr [[COPY1]], 1, [[COPY]]19 ; CHECK-NEXT: $q0 = COPY [[INSvi8gpr]]20 ; CHECK-NEXT: RET_ReallyLR implicit $q021 %0:gpr(s32) = COPY $w022 %trunc:gpr(s8) = G_TRUNC %023 %1:fpr(<16 x s8>) = COPY $q124 %3:gpr(s64) = G_CONSTANT i64 125 %4:gpr(s32) = G_ANYEXT %trunc26 %2:fpr(<16 x s8>) = G_INSERT_VECTOR_ELT %1, %4:gpr(s32), %3:gpr(s64)27 $q0 = COPY %2(<16 x s8>)28 RET_ReallyLR implicit $q029 30...31---32name: v8s8_gpr33alignment: 434legalized: true35regBankSelected: true36tracksRegLiveness: true37body: |38 bb.0:39 liveins: $d0, $w040 41 ; CHECK-LABEL: name: v8s8_gpr42 ; CHECK: liveins: $d0, $w043 ; CHECK-NEXT: {{ $}}44 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w045 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d046 ; CHECK-NEXT: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF47 ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY1]], %subreg.dsub48 ; CHECK-NEXT: [[INSvi8gpr:%[0-9]+]]:fpr128 = INSvi8gpr [[INSERT_SUBREG]], 1, [[COPY]]49 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr64 = COPY [[INSvi8gpr]].dsub50 ; CHECK-NEXT: $d0 = COPY [[COPY2]]51 ; CHECK-NEXT: RET_ReallyLR implicit $d052 %0:gpr(s32) = COPY $w053 %trunc:gpr(s8) = G_TRUNC %054 %1:fpr(<8 x s8>) = COPY $d055 %3:gpr(s64) = G_CONSTANT i64 156 %4:gpr(s32) = G_ANYEXT %trunc57 %2:fpr(<8 x s8>) = G_INSERT_VECTOR_ELT %1, %4(s32), %3(s64)58 $d0 = COPY %2(<8 x s8>)59 RET_ReallyLR implicit $d060 61...62---63name: v8s16_gpr64alignment: 465legalized: true66regBankSelected: true67tracksRegLiveness: true68body: |69 bb.0:70 liveins: $q1, $w071 72 ; CHECK-LABEL: name: v8s16_gpr73 ; CHECK: liveins: $q1, $w074 ; CHECK-NEXT: {{ $}}75 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w076 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q177 ; CHECK-NEXT: [[INSvi16gpr:%[0-9]+]]:fpr128 = INSvi16gpr [[COPY1]], 1, [[COPY]]78 ; CHECK-NEXT: $q0 = COPY [[INSvi16gpr]]79 ; CHECK-NEXT: RET_ReallyLR implicit $q080 %0:gpr(s32) = COPY $w081 %trunc:gpr(s16) = G_TRUNC %082 %1:fpr(<8 x s16>) = COPY $q183 %3:gpr(s64) = G_CONSTANT i64 184 %4:gpr(s32) = G_ANYEXT %trunc85 %2:fpr(<8 x s16>) = G_INSERT_VECTOR_ELT %1, %4:gpr(s32), %3:gpr(s64)86 $q0 = COPY %2(<8 x s16>)87 RET_ReallyLR implicit $q088 89...90---91name: v8s16_fpr92alignment: 493legalized: true94regBankSelected: true95tracksRegLiveness: true96body: |97 bb.0:98 liveins: $q1, $h099 100 ; CHECK-LABEL: name: v8s16_fpr101 ; CHECK: liveins: $q1, $h0102 ; CHECK-NEXT: {{ $}}103 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr16 = COPY $h0104 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1105 ; CHECK-NEXT: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF106 ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.hsub107 ; CHECK-NEXT: [[INSvi16lane:%[0-9]+]]:fpr128 = INSvi16lane [[COPY1]], 1, [[INSERT_SUBREG]], 0108 ; CHECK-NEXT: $q0 = COPY [[INSvi16lane]]109 ; CHECK-NEXT: RET_ReallyLR implicit $q0110 %0:fpr(s16) = COPY $h0111 %1:fpr(<8 x s16>) = COPY $q1112 %3:gpr(s64) = G_CONSTANT i64 1113 %2:fpr(<8 x s16>) = G_INSERT_VECTOR_ELT %1, %0(s16), %3(s64)114 $q0 = COPY %2(<8 x s16>)115 RET_ReallyLR implicit $q0116 117...118---119name: v4s32_fpr120alignment: 4121legalized: true122regBankSelected: true123tracksRegLiveness: true124body: |125 bb.0:126 liveins: $q1, $s0127 128 ; CHECK-LABEL: name: v4s32_fpr129 ; CHECK: liveins: $q1, $s0130 ; CHECK-NEXT: {{ $}}131 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $s0132 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1133 ; CHECK-NEXT: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF134 ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.ssub135 ; CHECK-NEXT: [[INSvi32lane:%[0-9]+]]:fpr128 = INSvi32lane [[COPY1]], 1, [[INSERT_SUBREG]], 0136 ; CHECK-NEXT: $q0 = COPY [[INSvi32lane]]137 ; CHECK-NEXT: RET_ReallyLR implicit $q0138 %0:fpr(s32) = COPY $s0139 %1:fpr(<4 x s32>) = COPY $q1140 %3:gpr(s64) = G_CONSTANT i64 1141 %2:fpr(<4 x s32>) = G_INSERT_VECTOR_ELT %1, %0(s32), %3(s64)142 $q0 = COPY %2(<4 x s32>)143 RET_ReallyLR implicit $q0144 145...146---147name: v4s32_gpr148alignment: 4149legalized: true150regBankSelected: true151tracksRegLiveness: true152body: |153 bb.0:154 liveins: $q0, $w0155 156 ; CHECK-LABEL: name: v4s32_gpr157 ; CHECK: liveins: $q0, $w0158 ; CHECK-NEXT: {{ $}}159 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0160 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0161 ; CHECK-NEXT: [[INSvi32gpr:%[0-9]+]]:fpr128 = INSvi32gpr [[COPY1]], 1, [[COPY]]162 ; CHECK-NEXT: $q0 = COPY [[INSvi32gpr]]163 ; CHECK-NEXT: RET_ReallyLR implicit $q0164 %0:gpr(s32) = COPY $w0165 %1:fpr(<4 x s32>) = COPY $q0166 %3:gpr(s64) = G_CONSTANT i64 1167 %2:fpr(<4 x s32>) = G_INSERT_VECTOR_ELT %1, %0(s32), %3(s64)168 $q0 = COPY %2(<4 x s32>)169 RET_ReallyLR implicit $q0170 171...172---173name: v4s16_gpr174alignment: 4175legalized: true176regBankSelected: true177tracksRegLiveness: true178body: |179 bb.0:180 liveins: $d0, $w0181 182 ; CHECK-LABEL: name: v4s16_gpr183 ; CHECK: liveins: $d0, $w0184 ; CHECK-NEXT: {{ $}}185 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0186 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0187 ; CHECK-NEXT: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF188 ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY1]], %subreg.dsub189 ; CHECK-NEXT: [[INSvi16gpr:%[0-9]+]]:fpr128 = INSvi16gpr [[INSERT_SUBREG]], 1, [[COPY]]190 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr64 = COPY [[INSvi16gpr]].dsub191 ; CHECK-NEXT: $d0 = COPY [[COPY2]]192 ; CHECK-NEXT: RET_ReallyLR implicit $d0193 %0:gpr(s32) = COPY $w0194 %trunc:gpr(s16) = G_TRUNC %0195 %1:fpr(<4 x s16>) = COPY $d0196 %3:gpr(s64) = G_CONSTANT i64 1197 %4:gpr(s32) = G_ANYEXT %trunc198 %2:fpr(<4 x s16>) = G_INSERT_VECTOR_ELT %1, %4(s32), %3(s64)199 $d0 = COPY %2(<4 x s16>)200 RET_ReallyLR implicit $d0201 202...203---204name: v2s64_fpr205alignment: 4206legalized: true207regBankSelected: true208tracksRegLiveness: true209body: |210 bb.0:211 liveins: $d0, $q1212 213 ; CHECK-LABEL: name: v2s64_fpr214 ; CHECK: liveins: $d0, $q1215 ; CHECK-NEXT: {{ $}}216 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0217 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1218 ; CHECK-NEXT: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF219 ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.dsub220 ; CHECK-NEXT: [[INSvi64lane:%[0-9]+]]:fpr128 = INSvi64lane [[COPY1]], 1, [[INSERT_SUBREG]], 0221 ; CHECK-NEXT: $q0 = COPY [[INSvi64lane]]222 ; CHECK-NEXT: RET_ReallyLR implicit $q0223 %0:fpr(s64) = COPY $d0224 %1:fpr(<2 x s64>) = COPY $q1225 %3:gpr(s64) = G_CONSTANT i64 1226 %2:fpr(<2 x s64>) = G_INSERT_VECTOR_ELT %1, %0(s64), %3(s64)227 $q0 = COPY %2(<2 x s64>)228 RET_ReallyLR implicit $q0229 230...231---232name: v2s64_gpr233alignment: 4234legalized: true235regBankSelected: true236tracksRegLiveness: true237body: |238 bb.0:239 liveins: $q0, $x0240 241 ; CHECK-LABEL: name: v2s64_gpr242 ; CHECK: liveins: $q0, $x0243 ; CHECK-NEXT: {{ $}}244 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0245 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0246 ; CHECK-NEXT: [[INSvi64gpr:%[0-9]+]]:fpr128 = INSvi64gpr [[COPY1]], 0, [[COPY]]247 ; CHECK-NEXT: $q0 = COPY [[INSvi64gpr]]248 ; CHECK-NEXT: RET_ReallyLR implicit $q0249 %0:gpr(s64) = COPY $x0250 %1:fpr(<2 x s64>) = COPY $q0251 %3:gpr(s64) = G_CONSTANT i64 0252 %2:fpr(<2 x s64>) = G_INSERT_VECTOR_ELT %1, %0(s64), %3(s64)253 $q0 = COPY %2(<2 x s64>)254 RET_ReallyLR implicit $q0255 256...257---258name: v2s32_fpr259alignment: 4260legalized: true261regBankSelected: true262tracksRegLiveness: true263body: |264 bb.0:265 liveins: $d1, $s0266 267 ; CHECK-LABEL: name: v2s32_fpr268 ; CHECK: liveins: $d1, $s0269 ; CHECK-NEXT: {{ $}}270 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $s0271 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1272 ; CHECK-NEXT: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF273 ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.ssub274 ; CHECK-NEXT: [[DEF1:%[0-9]+]]:fpr128 = IMPLICIT_DEF275 ; CHECK-NEXT: [[INSERT_SUBREG1:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF1]], [[COPY1]], %subreg.dsub276 ; CHECK-NEXT: [[INSvi32lane:%[0-9]+]]:fpr128 = INSvi32lane [[INSERT_SUBREG1]], 1, [[INSERT_SUBREG]], 0277 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr64 = COPY [[INSvi32lane]].dsub278 ; CHECK-NEXT: $d0 = COPY [[COPY2]]279 ; CHECK-NEXT: RET_ReallyLR implicit $d0280 %0:fpr(s32) = COPY $s0281 %1:fpr(<2 x s32>) = COPY $d1282 %3:gpr(s64) = G_CONSTANT i64 1283 %2:fpr(<2 x s32>) = G_INSERT_VECTOR_ELT %1, %0(s32), %3(s64)284 $d0 = COPY %2(<2 x s32>)285 RET_ReallyLR implicit $d0286 287...288---289name: v2s32_gpr290alignment: 4291legalized: true292regBankSelected: true293tracksRegLiveness: true294body: |295 bb.0:296 liveins: $d0, $w0297 298 ; CHECK-LABEL: name: v2s32_gpr299 ; CHECK: liveins: $d0, $w0300 ; CHECK-NEXT: {{ $}}301 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0302 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0303 ; CHECK-NEXT: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF304 ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY1]], %subreg.dsub305 ; CHECK-NEXT: [[INSvi32gpr:%[0-9]+]]:fpr128 = INSvi32gpr [[INSERT_SUBREG]], 1, [[COPY]]306 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr64 = COPY [[INSvi32gpr]].dsub307 ; CHECK-NEXT: $d0 = COPY [[COPY2]]308 ; CHECK-NEXT: RET_ReallyLR implicit $d0309 %0:gpr(s32) = COPY $w0310 %1:fpr(<2 x s32>) = COPY $d0311 %3:gpr(s64) = G_CONSTANT i64 1312 %2:fpr(<2 x s32>) = G_INSERT_VECTOR_ELT %1, %0(s32), %3(s64)313 $d0 = COPY %2(<2 x s32>)314 RET_ReallyLR implicit $d0315 316...317