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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s3 4--- |5 target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"6 7 define void @anyext_s64_from_s32() { ret void }8 define void @anyext_s32_from_s8() { ret void }9 define void @anyext_v8s16_from_v8s8() { ret void }10 define void @anyext_v4s32_from_v4s16() { ret void }11 define void @anyext_v2s64_from_v2s32() { ret void }12 13 define void @zext_s64_from_s32() { ret void }14 define void @zext_s32_from_s16() { ret void }15 define void @zext_s32_from_s8() { ret void }16 define void @zext_s16_from_s8() { ret void }17 define void @zext_v8s16_from_v8s8() { ret void }18 define void @zext_v4s32_from_v4s16() { ret void }19 define void @zext_v2s64_from_v2s32() { ret void }20 21 define void @sext_s64_from_s32() { ret void }22 define void @sext_s32_from_s16() { ret void }23 define void @sext_s32_from_s8() { ret void }24 define void @sext_s16_from_s8() { ret void }25 define void @sext_v8s16_from_v8s8() { ret void }26 define void @sext_v4s32_from_v4s16() { ret void }27 define void @sext_v2s64_from_v2s32() { ret void }28...29 30---31name: anyext_s64_from_s3232legalized: true33regBankSelected: true34 35registers:36 - { id: 0, class: gpr }37 - { id: 1, class: gpr }38 39body: |40 bb.0:41 liveins: $w042 43 ; CHECK-LABEL: name: anyext_s64_from_s3244 ; CHECK: liveins: $w045 ; CHECK-NEXT: {{ $}}46 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w047 ; CHECK-NEXT: [[DEF:%[0-9]+]]:gpr64all = IMPLICIT_DEF48 ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:gpr64all = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.sub_3249 ; CHECK-NEXT: $x0 = COPY [[INSERT_SUBREG]]50 %0(s32) = COPY $w051 %1(s64) = G_ANYEXT %052 $x0 = COPY %1(s64)53...54 55---56name: anyext_s32_from_s857legalized: true58regBankSelected: true59 60registers:61 - { id: 0, class: gpr }62 - { id: 1, class: gpr }63 64body: |65 bb.0:66 liveins: $w067 68 ; CHECK-LABEL: name: anyext_s32_from_s869 ; CHECK: liveins: $w070 ; CHECK-NEXT: {{ $}}71 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w072 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32all = COPY [[COPY]]73 ; CHECK-NEXT: $w0 = COPY [[COPY1]]74 %2:gpr(s32) = COPY $w075 %0(s8) = G_TRUNC %276 %1(s32) = G_ANYEXT %077 $w0 = COPY %1(s32)78...79 80---81name: anyext_v8s16_from_v8s882alignment: 483legalized: true84regBankSelected: true85tracksRegLiveness: true86registers:87 - { id: 0, class: fpr }88 - { id: 1, class: fpr }89machineFunctionInfo: {}90body: |91 bb.0:92 liveins: $d093 94 ; CHECK-LABEL: name: anyext_v8s16_from_v8s895 ; CHECK: liveins: $d096 ; CHECK-NEXT: {{ $}}97 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d098 ; CHECK-NEXT: [[USHLLv8i8_shift:%[0-9]+]]:fpr128 = USHLLv8i8_shift [[COPY]], 099 ; CHECK-NEXT: $q0 = COPY [[USHLLv8i8_shift]]100 ; CHECK-NEXT: RET_ReallyLR implicit $q0101 %0:fpr(<8 x s8>) = COPY $d0102 %1:fpr(<8 x s16>) = G_ANYEXT %0(<8 x s8>)103 $q0 = COPY %1(<8 x s16>)104 RET_ReallyLR implicit $q0105...106 107---108name: anyext_v4s32_from_v4s16109alignment: 4110legalized: true111regBankSelected: true112tracksRegLiveness: true113registers:114 - { id: 0, class: fpr }115 - { id: 1, class: fpr }116machineFunctionInfo: {}117body: |118 bb.0:119 liveins: $d0120 121 ; CHECK-LABEL: name: anyext_v4s32_from_v4s16122 ; CHECK: liveins: $d0123 ; CHECK-NEXT: {{ $}}124 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0125 ; CHECK-NEXT: [[USHLLv4i16_shift:%[0-9]+]]:fpr128 = USHLLv4i16_shift [[COPY]], 0126 ; CHECK-NEXT: $q0 = COPY [[USHLLv4i16_shift]]127 ; CHECK-NEXT: RET_ReallyLR implicit $q0128 %0:fpr(<4 x s16>) = COPY $d0129 %1:fpr(<4 x s32>) = G_ANYEXT %0(<4 x s16>)130 $q0 = COPY %1(<4 x s32>)131 RET_ReallyLR implicit $q0132...133 134---135name: anyext_v2s64_from_v2s32136alignment: 4137legalized: true138regBankSelected: true139tracksRegLiveness: true140registers:141 - { id: 0, class: fpr }142 - { id: 1, class: fpr }143machineFunctionInfo: {}144body: |145 bb.0:146 liveins: $d0147 148 ; CHECK-LABEL: name: anyext_v2s64_from_v2s32149 ; CHECK: liveins: $d0150 ; CHECK-NEXT: {{ $}}151 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0152 ; CHECK-NEXT: [[USHLLv2i32_shift:%[0-9]+]]:fpr128 = USHLLv2i32_shift [[COPY]], 0153 ; CHECK-NEXT: $q0 = COPY [[USHLLv2i32_shift]]154 ; CHECK-NEXT: RET_ReallyLR implicit $q0155 %0:fpr(<2 x s32>) = COPY $d0156 %1:fpr(<2 x s64>) = G_ANYEXT %0(<2 x s32>)157 $q0 = COPY %1(<2 x s64>)158 RET_ReallyLR implicit $q0159...160 161---162name: zext_s64_from_s32163legalized: true164regBankSelected: true165 166registers:167 - { id: 0, class: gpr }168 - { id: 1, class: gpr }169 170body: |171 bb.0:172 liveins: $w0173 174 ; CHECK-LABEL: name: zext_s64_from_s32175 ; CHECK: liveins: $w0176 ; CHECK-NEXT: {{ $}}177 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0178 ; CHECK-NEXT: [[ORRWrs:%[0-9]+]]:gpr32 = ORRWrs $wzr, [[COPY]], 0179 ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[ORRWrs]], %subreg.sub_32180 ; CHECK-NEXT: $x0 = COPY [[SUBREG_TO_REG]]181 %0(s32) = COPY $w0182 %1(s64) = G_ZEXT %0183 $x0 = COPY %1(s64)184...185 186---187name: zext_s32_from_s16188legalized: true189regBankSelected: true190 191registers:192 - { id: 0, class: gpr }193 - { id: 1, class: gpr }194 195body: |196 bb.0:197 liveins: $w0198 199 ; CHECK-LABEL: name: zext_s32_from_s16200 ; CHECK: liveins: $w0201 ; CHECK-NEXT: {{ $}}202 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0203 ; CHECK-NEXT: [[UBFMWri:%[0-9]+]]:gpr32 = UBFMWri [[COPY]], 0, 15204 ; CHECK-NEXT: $w0 = COPY [[UBFMWri]]205 %2:gpr(s32) = COPY $w0206 %0(s16) = G_TRUNC %2207 %1(s32) = G_ZEXT %0208 $w0 = COPY %1209...210 211---212name: zext_s32_from_s8213legalized: true214regBankSelected: true215 216registers:217 - { id: 0, class: gpr }218 - { id: 1, class: gpr }219 220body: |221 bb.0:222 liveins: $w0223 224 ; CHECK-LABEL: name: zext_s32_from_s8225 ; CHECK: liveins: $w0226 ; CHECK-NEXT: {{ $}}227 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0228 ; CHECK-NEXT: [[UBFMWri:%[0-9]+]]:gpr32 = UBFMWri [[COPY]], 0, 15229 ; CHECK-NEXT: $w0 = COPY [[UBFMWri]]230 %2:gpr(s32) = COPY $w0231 %0(s16) = G_TRUNC %2232 %1(s32) = G_ZEXT %0233 $w0 = COPY %1(s32)234...235 236---237name: zext_s16_from_s8238legalized: true239regBankSelected: true240 241registers:242 - { id: 0, class: gpr }243 - { id: 1, class: gpr }244 245body: |246 bb.0:247 liveins: $w0248 249 ; CHECK-LABEL: name: zext_s16_from_s8250 ; CHECK: liveins: $w0251 ; CHECK-NEXT: {{ $}}252 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0253 ; CHECK-NEXT: [[UBFMWri:%[0-9]+]]:gpr32 = UBFMWri [[COPY]], 0, 7254 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32all = COPY [[UBFMWri]]255 ; CHECK-NEXT: $w0 = COPY [[COPY1]]256 %2:gpr(s32) = COPY $w0257 %0(s8) = G_TRUNC %2258 %1(s16) = G_ZEXT %0259 %3:gpr(s32) = G_ANYEXT %1260 $w0 = COPY %3(s32)261...262 263---264name: zext_v8s16_from_v8s8265alignment: 4266legalized: true267regBankSelected: true268tracksRegLiveness: true269registers:270 - { id: 0, class: fpr }271 - { id: 1, class: fpr }272machineFunctionInfo: {}273body: |274 bb.0:275 liveins: $d0276 277 ; CHECK-LABEL: name: zext_v8s16_from_v8s8278 ; CHECK: liveins: $d0279 ; CHECK-NEXT: {{ $}}280 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0281 ; CHECK-NEXT: [[USHLLv8i8_shift:%[0-9]+]]:fpr128 = USHLLv8i8_shift [[COPY]], 0282 ; CHECK-NEXT: $q0 = COPY [[USHLLv8i8_shift]]283 ; CHECK-NEXT: RET_ReallyLR implicit $q0284 %0:fpr(<8 x s8>) = COPY $d0285 %1:fpr(<8 x s16>) = G_ZEXT %0(<8 x s8>)286 $q0 = COPY %1(<8 x s16>)287 RET_ReallyLR implicit $q0288 289...290 291---292name: zext_v4s32_from_v4s16293alignment: 4294legalized: true295regBankSelected: true296tracksRegLiveness: true297registers:298 - { id: 0, class: fpr }299 - { id: 1, class: fpr }300machineFunctionInfo: {}301body: |302 bb.0:303 liveins: $d0304 305 ; CHECK-LABEL: name: zext_v4s32_from_v4s16306 ; CHECK: liveins: $d0307 ; CHECK-NEXT: {{ $}}308 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0309 ; CHECK-NEXT: [[USHLLv4i16_shift:%[0-9]+]]:fpr128 = USHLLv4i16_shift [[COPY]], 0310 ; CHECK-NEXT: $q0 = COPY [[USHLLv4i16_shift]]311 ; CHECK-NEXT: RET_ReallyLR implicit $q0312 %0:fpr(<4 x s16>) = COPY $d0313 %1:fpr(<4 x s32>) = G_ZEXT %0(<4 x s16>)314 $q0 = COPY %1(<4 x s32>)315 RET_ReallyLR implicit $q0316...317 318---319name: zext_v2s64_from_v2s32320alignment: 4321legalized: true322regBankSelected: true323tracksRegLiveness: true324registers:325 - { id: 0, class: fpr }326 - { id: 1, class: fpr }327machineFunctionInfo: {}328body: |329 bb.0:330 liveins: $d0331 332 ; CHECK-LABEL: name: zext_v2s64_from_v2s32333 ; CHECK: liveins: $d0334 ; CHECK-NEXT: {{ $}}335 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0336 ; CHECK-NEXT: [[USHLLv2i32_shift:%[0-9]+]]:fpr128 = USHLLv2i32_shift [[COPY]], 0337 ; CHECK-NEXT: $q0 = COPY [[USHLLv2i32_shift]]338 ; CHECK-NEXT: RET_ReallyLR implicit $q0339 %0:fpr(<2 x s32>) = COPY $d0340 %1:fpr(<2 x s64>) = G_ZEXT %0(<2 x s32>)341 $q0 = COPY %1(<2 x s64>)342 RET_ReallyLR implicit $q0343...344 345---346name: sext_s64_from_s32347legalized: true348regBankSelected: true349 350registers:351 - { id: 0, class: gpr }352 - { id: 1, class: gpr }353 354body: |355 bb.0:356 liveins: $w0357 358 ; CHECK-LABEL: name: sext_s64_from_s32359 ; CHECK: liveins: $w0360 ; CHECK-NEXT: {{ $}}361 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0362 ; CHECK-NEXT: [[DEF:%[0-9]+]]:gpr64all = IMPLICIT_DEF363 ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:gpr64 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.sub_32364 ; CHECK-NEXT: [[SBFMXri:%[0-9]+]]:gpr64 = SBFMXri [[INSERT_SUBREG]], 0, 31365 ; CHECK-NEXT: $x0 = COPY [[SBFMXri]]366 %0(s32) = COPY $w0367 %1(s64) = G_SEXT %0368 $x0 = COPY %1(s64)369...370 371---372name: sext_s32_from_s16373legalized: true374regBankSelected: true375 376registers:377 - { id: 0, class: gpr }378 - { id: 1, class: gpr }379 380body: |381 bb.0:382 liveins: $w0383 384 ; CHECK-LABEL: name: sext_s32_from_s16385 ; CHECK: liveins: $w0386 ; CHECK-NEXT: {{ $}}387 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0388 ; CHECK-NEXT: [[SBFMWri:%[0-9]+]]:gpr32 = SBFMWri [[COPY]], 0, 15389 ; CHECK-NEXT: $w0 = COPY [[SBFMWri]]390 %2:gpr(s32) = COPY $w0391 %0(s16) = G_TRUNC %2392 %1(s32) = G_SEXT %0393 $w0 = COPY %1394...395 396---397name: sext_s32_from_s8398legalized: true399regBankSelected: true400 401registers:402 - { id: 0, class: gpr }403 - { id: 1, class: gpr }404 405body: |406 bb.0:407 liveins: $w0408 409 ; CHECK-LABEL: name: sext_s32_from_s8410 ; CHECK: liveins: $w0411 ; CHECK-NEXT: {{ $}}412 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0413 ; CHECK-NEXT: [[SBFMWri:%[0-9]+]]:gpr32 = SBFMWri [[COPY]], 0, 7414 ; CHECK-NEXT: $w0 = COPY [[SBFMWri]]415 %2:gpr(s32) = COPY $w0416 %0(s8) = G_TRUNC %2417 %1(s32) = G_SEXT %0418 $w0 = COPY %1(s32)419...420 421---422name: sext_s16_from_s8423legalized: true424regBankSelected: true425 426registers:427 - { id: 0, class: gpr }428 - { id: 1, class: gpr }429 430body: |431 bb.0:432 liveins: $w0433 434 ; CHECK-LABEL: name: sext_s16_from_s8435 ; CHECK: liveins: $w0436 ; CHECK-NEXT: {{ $}}437 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0438 ; CHECK-NEXT: [[SBFMWri:%[0-9]+]]:gpr32 = SBFMWri [[COPY]], 0, 7439 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32all = COPY [[SBFMWri]]440 ; CHECK-NEXT: $w0 = COPY [[COPY1]]441 %2:gpr(s32) = COPY $w0442 %0(s8) = G_TRUNC %2443 %1(s16) = G_SEXT %0444 %3:gpr(s32) = G_ANYEXT %1445 $w0 = COPY %3(s32)446...447 448---449name: sext_v8s16_from_v8s8450alignment: 4451legalized: true452regBankSelected: true453tracksRegLiveness: true454registers:455 - { id: 0, class: fpr }456 - { id: 1, class: fpr }457machineFunctionInfo: {}458body: |459 bb.0:460 liveins: $d0461 462 ; CHECK-LABEL: name: sext_v8s16_from_v8s8463 ; CHECK: liveins: $d0464 ; CHECK-NEXT: {{ $}}465 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0466 ; CHECK-NEXT: [[SSHLLv8i8_shift:%[0-9]+]]:fpr128 = SSHLLv8i8_shift [[COPY]], 0467 ; CHECK-NEXT: $q0 = COPY [[SSHLLv8i8_shift]]468 ; CHECK-NEXT: RET_ReallyLR implicit $q0469 %0:fpr(<8 x s8>) = COPY $d0470 %1:fpr(<8 x s16>) = G_SEXT %0(<8 x s8>)471 $q0 = COPY %1(<8 x s16>)472 RET_ReallyLR implicit $q0473 474...475 476---477name: sext_v4s32_from_v4s16478alignment: 4479legalized: true480regBankSelected: true481tracksRegLiveness: true482registers:483 - { id: 0, class: fpr }484 - { id: 1, class: fpr }485machineFunctionInfo: {}486body: |487 bb.0:488 liveins: $d0489 490 ; CHECK-LABEL: name: sext_v4s32_from_v4s16491 ; CHECK: liveins: $d0492 ; CHECK-NEXT: {{ $}}493 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0494 ; CHECK-NEXT: [[SSHLLv4i16_shift:%[0-9]+]]:fpr128 = SSHLLv4i16_shift [[COPY]], 0495 ; CHECK-NEXT: $q0 = COPY [[SSHLLv4i16_shift]]496 ; CHECK-NEXT: RET_ReallyLR implicit $q0497 %0:fpr(<4 x s16>) = COPY $d0498 %1:fpr(<4 x s32>) = G_SEXT %0(<4 x s16>)499 $q0 = COPY %1(<4 x s32>)500 RET_ReallyLR implicit $q0501...502 503---504name: sext_v2s64_from_v2s32505alignment: 4506legalized: true507regBankSelected: true508tracksRegLiveness: true509registers:510 - { id: 0, class: fpr }511 - { id: 1, class: fpr }512machineFunctionInfo: {}513body: |514 bb.0:515 liveins: $d0516 517 ; CHECK-LABEL: name: sext_v2s64_from_v2s32518 ; CHECK: liveins: $d0519 ; CHECK-NEXT: {{ $}}520 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0521 ; CHECK-NEXT: [[SSHLLv2i32_shift:%[0-9]+]]:fpr128 = SSHLLv2i32_shift [[COPY]], 0522 ; CHECK-NEXT: $q0 = COPY [[SSHLLv2i32_shift]]523 ; CHECK-NEXT: RET_ReallyLR implicit $q0524 %0:fpr(<2 x s32>) = COPY $d0525 %1:fpr(<2 x s64>) = G_SEXT %0(<2 x s32>)526 $q0 = COPY %1(<2 x s64>)527 RET_ReallyLR implicit $q0528