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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s3 4--- |5 target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"6 7 define void @sdiv_s32_gpr() { ret void }8...9 10---11# Check that we select a 32-bit GPR sdiv intrinsic into SDIVWrr for GPR32.12# Also check that we constrain the register class of the COPY to GPR32.13name: sdiv_s32_gpr14legalized: true15regBankSelected: true16 17registers:18 - { id: 0, class: gpr }19 - { id: 1, class: gpr }20 - { id: 2, class: gpr }21 22body: |23 bb.0:24 liveins: $w0, $w125 26 ; CHECK-LABEL: name: sdiv_s32_gpr27 ; CHECK: liveins: $w0, $w128 ; CHECK-NEXT: {{ $}}29 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w030 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w131 ; CHECK-NEXT: [[SDIVWr:%[0-9]+]]:gpr32 = SDIVWr [[COPY]], [[COPY1]]32 ; CHECK-NEXT: $w0 = COPY [[SDIVWr]]33 %0(s32) = COPY $w034 %1(s32) = COPY $w135 %2(s32) = G_INTRINSIC intrinsic(@llvm.aarch64.sdiv.i32), %0, %136 $w0 = COPY %2(s32)37...38