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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=aarch64-- -mattr=+aes,+fuse-aes -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s3 4---5# Check that we select the aarch64_crypto_aesmc and aarch64_crypto_aese6# intrinsics into an ARSMCrrTied and AESErr instruction sequence.7name: aesmc_aese8legalized: true9regBankSelected: true10 11body: |12 bb.0:13 liveins: $q0, $q114 15 ; CHECK-LABEL: name: aesmc_aese16 ; CHECK: liveins: $q0, $q117 ; CHECK-NEXT: {{ $}}18 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q019 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q120 ; CHECK-NEXT: [[AESErr:%[0-9]+]]:fpr128 = AESErr [[COPY]], [[COPY1]]21 ; CHECK-NEXT: [[AESMCrrTied:%[0-9]+]]:fpr128 = AESMCrrTied [[AESErr]]22 ; CHECK-NEXT: $q0 = COPY [[AESMCrrTied]]23 %0:fpr(<16 x s8>) = COPY $q024 %1:fpr(<16 x s8>) = COPY $q125 %2:fpr(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.aarch64.crypto.aese), %0, %126 %3:fpr(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.aarch64.crypto.aesmc), %227 $q0 = COPY %3(<16 x s8>)28...29