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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc %s -verify-machineinstrs -mtriple=aarch64-unknown-unknown -run-pass=instruction-select -mattr=+fullfp16 -o - | FileCheck %s3 4...5---6name: test_f64.intrinsic_round7alignment: 48legalized: true9regBankSelected: true10tracksRegLiveness: true11machineFunctionInfo: {}12body: |13 bb.0:14 liveins: $d015 16 ; CHECK-LABEL: name: test_f64.intrinsic_round17 ; CHECK: liveins: $d018 ; CHECK-NEXT: {{ $}}19 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d020 ; CHECK-NEXT: [[FRINTADr:%[0-9]+]]:fpr64 = nofpexcept FRINTADr [[COPY]], implicit $fpcr21 ; CHECK-NEXT: $d0 = COPY [[FRINTADr]]22 ; CHECK-NEXT: RET_ReallyLR implicit $d023 %0:fpr(s64) = COPY $d024 %1:fpr(s64) = G_INTRINSIC_ROUND %025 $d0 = COPY %1(s64)26 RET_ReallyLR implicit $d027 28...29---30name: test_f32.intrinsic_round31alignment: 432legalized: true33regBankSelected: true34tracksRegLiveness: true35machineFunctionInfo: {}36body: |37 bb.0:38 liveins: $s039 40 ; CHECK-LABEL: name: test_f32.intrinsic_round41 ; CHECK: liveins: $s042 ; CHECK-NEXT: {{ $}}43 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $s044 ; CHECK-NEXT: [[FRINTASr:%[0-9]+]]:fpr32 = nofpexcept FRINTASr [[COPY]], implicit $fpcr45 ; CHECK-NEXT: $s0 = COPY [[FRINTASr]]46 ; CHECK-NEXT: RET_ReallyLR implicit $s047 %0:fpr(s32) = COPY $s048 %1:fpr(s32) = G_INTRINSIC_ROUND %049 $s0 = COPY %1(s32)50 RET_ReallyLR implicit $s051 52...53---54name: test_f16.intrinsic_round55alignment: 456legalized: true57regBankSelected: true58tracksRegLiveness: true59frameInfo:60 maxCallFrameSize: 061machineFunctionInfo: {}62body: |63 bb.0:64 liveins: $h065 66 ; CHECK-LABEL: name: test_f16.intrinsic_round67 ; CHECK: liveins: $h068 ; CHECK-NEXT: {{ $}}69 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr16 = COPY $h070 ; CHECK-NEXT: [[FRINTAHr:%[0-9]+]]:fpr16 = nofpexcept FRINTAHr [[COPY]], implicit $fpcr71 ; CHECK-NEXT: $h0 = COPY [[FRINTAHr]]72 ; CHECK-NEXT: RET_ReallyLR implicit $h073 %0:fpr(s16) = COPY $h074 %1:fpr(s16) = G_INTRINSIC_ROUND %075 $h0 = COPY %1(s16)76 RET_ReallyLR implicit $h077 78...79---80name: test_v4f16.intrinsic_round81alignment: 482legalized: true83regBankSelected: true84tracksRegLiveness: true85frameInfo:86 maxCallFrameSize: 087machineFunctionInfo: {}88body: |89 bb.0:90 liveins: $d091 92 ; CHECK-LABEL: name: test_v4f16.intrinsic_round93 ; CHECK: liveins: $d094 ; CHECK-NEXT: {{ $}}95 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d096 ; CHECK-NEXT: [[FRINTAv4f16_:%[0-9]+]]:fpr64 = nofpexcept FRINTAv4f16 [[COPY]], implicit $fpcr97 ; CHECK-NEXT: $d0 = COPY [[FRINTAv4f16_]]98 ; CHECK-NEXT: RET_ReallyLR implicit $d099 %0:fpr(<4 x s16>) = COPY $d0100 %1:fpr(<4 x s16>) = G_INTRINSIC_ROUND %0101 $d0 = COPY %1(<4 x s16>)102 RET_ReallyLR implicit $d0103 104...105---106name: test_v8f16.intrinsic_round107alignment: 4108legalized: true109regBankSelected: true110tracksRegLiveness: true111frameInfo:112 maxCallFrameSize: 0113machineFunctionInfo: {}114body: |115 bb.0:116 liveins: $q0117 118 ; CHECK-LABEL: name: test_v8f16.intrinsic_round119 ; CHECK: liveins: $q0120 ; CHECK-NEXT: {{ $}}121 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0122 ; CHECK-NEXT: [[FRINTAv8f16_:%[0-9]+]]:fpr128 = nofpexcept FRINTAv8f16 [[COPY]], implicit $fpcr123 ; CHECK-NEXT: $q0 = COPY [[FRINTAv8f16_]]124 ; CHECK-NEXT: RET_ReallyLR implicit $q0125 %0:fpr(<8 x s16>) = COPY $q0126 %1:fpr(<8 x s16>) = G_INTRINSIC_ROUND %0127 $q0 = COPY %1(<8 x s16>)128 RET_ReallyLR implicit $q0129 130...131---132name: test_v2f32.intrinsic_round133alignment: 4134legalized: true135regBankSelected: true136tracksRegLiveness: true137frameInfo:138 maxCallFrameSize: 0139machineFunctionInfo: {}140body: |141 bb.0:142 liveins: $d0143 144 ; CHECK-LABEL: name: test_v2f32.intrinsic_round145 ; CHECK: liveins: $d0146 ; CHECK-NEXT: {{ $}}147 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0148 ; CHECK-NEXT: [[FRINTAv2f32_:%[0-9]+]]:fpr64 = nofpexcept FRINTAv2f32 [[COPY]], implicit $fpcr149 ; CHECK-NEXT: $d0 = COPY [[FRINTAv2f32_]]150 ; CHECK-NEXT: RET_ReallyLR implicit $d0151 %0:fpr(<2 x s32>) = COPY $d0152 %1:fpr(<2 x s32>) = G_INTRINSIC_ROUND %0153 $d0 = COPY %1(<2 x s32>)154 RET_ReallyLR implicit $d0155 156...157---158name: test_v4f32.intrinsic_round159alignment: 4160legalized: true161regBankSelected: true162tracksRegLiveness: true163frameInfo:164 maxCallFrameSize: 0165machineFunctionInfo: {}166body: |167 bb.0:168 liveins: $q0169 170 ; CHECK-LABEL: name: test_v4f32.intrinsic_round171 ; CHECK: liveins: $q0172 ; CHECK-NEXT: {{ $}}173 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0174 ; CHECK-NEXT: [[FRINTAv4f32_:%[0-9]+]]:fpr128 = nofpexcept FRINTAv4f32 [[COPY]], implicit $fpcr175 ; CHECK-NEXT: $q0 = COPY [[FRINTAv4f32_]]176 ; CHECK-NEXT: RET_ReallyLR implicit $q0177 %0:fpr(<4 x s32>) = COPY $q0178 %1:fpr(<4 x s32>) = G_INTRINSIC_ROUND %0179 $q0 = COPY %1(<4 x s32>)180 RET_ReallyLR implicit $q0181 182...183---184name: test_v2f64.intrinsic_round185alignment: 4186legalized: true187regBankSelected: true188tracksRegLiveness: true189frameInfo:190 maxCallFrameSize: 0191machineFunctionInfo: {}192body: |193 bb.0:194 liveins: $q0195 196 ; CHECK-LABEL: name: test_v2f64.intrinsic_round197 ; CHECK: liveins: $q0198 ; CHECK-NEXT: {{ $}}199 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0200 ; CHECK-NEXT: [[FRINTAv2f64_:%[0-9]+]]:fpr128 = nofpexcept FRINTAv2f64 [[COPY]], implicit $fpcr201 ; CHECK-NEXT: $q0 = COPY [[FRINTAv2f64_]]202 ; CHECK-NEXT: RET_ReallyLR implicit $q0203 %0:fpr(<2 x s64>) = COPY $q0204 %1:fpr(<2 x s64>) = G_INTRINSIC_ROUND %0205 $q0 = COPY %1(<2 x s64>)206 RET_ReallyLR implicit $q0207