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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=aarch64 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s3...4---5name: LD2Twov8b6legalized: true7regBankSelected: true8tracksRegLiveness: true9body: |10 bb.0:11 liveins: $x0, $x1, $x212 ; CHECK-LABEL: name: LD2Twov8b13 ; CHECK: liveins: $x0, $x1, $x214 ; CHECK-NEXT: {{ $}}15 ; CHECK-NEXT: %ptr:gpr64sp = COPY $x016 ; CHECK-NEXT: [[LD2Twov8b:%[0-9]+]]:dd = LD2Twov8b %ptr :: (load (<8 x s64>))17 ; CHECK-NEXT: %dst1:fpr64 = COPY [[LD2Twov8b]].dsub018 ; CHECK-NEXT: %dst2:fpr64 = COPY [[LD2Twov8b]].dsub119 ; CHECK-NEXT: $d0 = COPY %dst120 ; CHECK-NEXT: $d1 = COPY %dst221 ; CHECK-NEXT: RET_ReallyLR implicit $d0, implicit $d122 %ptr:gpr(p0) = COPY $x023 %dst1:fpr(<8 x s8>), %dst2:fpr(<8 x s8>) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.neon.ld2), %ptr(p0) :: (load (<8 x s64>))24 $d0 = COPY %dst1(<8 x s8>)25 $d1 = COPY %dst2(<8 x s8>)26 RET_ReallyLR implicit $d0, implicit $d127...28---29name: LD2Twov16b30legalized: true31regBankSelected: true32tracksRegLiveness: true33body: |34 bb.0:35 liveins: $x0, $x1, $x236 ; CHECK-LABEL: name: LD2Twov16b37 ; CHECK: liveins: $x0, $x1, $x238 ; CHECK-NEXT: {{ $}}39 ; CHECK-NEXT: %ptr:gpr64sp = COPY $x040 ; CHECK-NEXT: [[LD2Twov16b:%[0-9]+]]:qq = LD2Twov16b %ptr :: (load (<16 x s64>))41 ; CHECK-NEXT: %dst1:fpr128 = COPY [[LD2Twov16b]].qsub042 ; CHECK-NEXT: %dst2:fpr128 = COPY [[LD2Twov16b]].qsub143 ; CHECK-NEXT: $q0 = COPY %dst144 ; CHECK-NEXT: $q1 = COPY %dst245 ; CHECK-NEXT: RET_ReallyLR implicit $q0, implicit $q146 %ptr:gpr(p0) = COPY $x047 %dst1:fpr(<16 x s8>), %dst2:fpr(<16 x s8>) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.neon.ld2), %ptr(p0) :: (load (<16 x s64>))48 $q0 = COPY %dst1(<16 x s8>)49 $q1 = COPY %dst2(<16 x s8>)50 RET_ReallyLR implicit $q0, implicit $q151...52---53name: LD2Twov4h54legalized: true55regBankSelected: true56tracksRegLiveness: true57body: |58 bb.0:59 liveins: $x0, $x1, $x260 ; CHECK-LABEL: name: LD2Twov4h61 ; CHECK: liveins: $x0, $x1, $x262 ; CHECK-NEXT: {{ $}}63 ; CHECK-NEXT: %ptr:gpr64sp = COPY $x064 ; CHECK-NEXT: [[LD2Twov4h:%[0-9]+]]:dd = LD2Twov4h %ptr :: (load (<4 x s64>))65 ; CHECK-NEXT: %dst1:fpr64 = COPY [[LD2Twov4h]].dsub066 ; CHECK-NEXT: %dst2:fpr64 = COPY [[LD2Twov4h]].dsub167 ; CHECK-NEXT: $d0 = COPY %dst168 ; CHECK-NEXT: $d1 = COPY %dst269 ; CHECK-NEXT: RET_ReallyLR implicit $d0, implicit $d170 %ptr:gpr(p0) = COPY $x071 %dst1:fpr(<4 x s16>), %dst2:fpr(<4 x s16>) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.neon.ld2), %ptr(p0) :: (load (<4 x s64>))72 $d0 = COPY %dst1(<4 x s16>)73 $d1 = COPY %dst2(<4 x s16>)74 RET_ReallyLR implicit $d0, implicit $d175...76---77name: LD2Twov8h78legalized: true79regBankSelected: true80tracksRegLiveness: true81body: |82 bb.0:83 liveins: $x0, $x1, $x284 ; CHECK-LABEL: name: LD2Twov8h85 ; CHECK: liveins: $x0, $x1, $x286 ; CHECK-NEXT: {{ $}}87 ; CHECK-NEXT: %ptr:gpr64sp = COPY $x088 ; CHECK-NEXT: [[LD2Twov8h:%[0-9]+]]:qq = LD2Twov8h %ptr :: (load (<8 x s64>))89 ; CHECK-NEXT: %dst1:fpr128 = COPY [[LD2Twov8h]].qsub090 ; CHECK-NEXT: %dst2:fpr128 = COPY [[LD2Twov8h]].qsub191 ; CHECK-NEXT: $q0 = COPY %dst192 ; CHECK-NEXT: $q1 = COPY %dst293 ; CHECK-NEXT: RET_ReallyLR implicit $q0, implicit $q194 %ptr:gpr(p0) = COPY $x095 %dst1:fpr(<8 x s16>), %dst2:fpr(<8 x s16>) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.neon.ld2), %ptr(p0) :: (load (<8 x s64>))96 $q0 = COPY %dst1(<8 x s16>)97 $q1 = COPY %dst2(<8 x s16>)98 RET_ReallyLR implicit $q0, implicit $q199...100---101name: LD2Twov2s102legalized: true103regBankSelected: true104tracksRegLiveness: true105body: |106 bb.0:107 liveins: $x0, $x1, $x2108 ; CHECK-LABEL: name: LD2Twov2s109 ; CHECK: liveins: $x0, $x1, $x2110 ; CHECK-NEXT: {{ $}}111 ; CHECK-NEXT: %ptr:gpr64sp = COPY $x0112 ; CHECK-NEXT: [[LD2Twov2s:%[0-9]+]]:dd = LD2Twov2s %ptr :: (load (<2 x s64>))113 ; CHECK-NEXT: %dst1:fpr64 = COPY [[LD2Twov2s]].dsub0114 ; CHECK-NEXT: %dst2:fpr64 = COPY [[LD2Twov2s]].dsub1115 ; CHECK-NEXT: $d0 = COPY %dst1116 ; CHECK-NEXT: $d1 = COPY %dst2117 ; CHECK-NEXT: RET_ReallyLR implicit $d0, implicit $d1118 %ptr:gpr(p0) = COPY $x0119 %dst1:fpr(<2 x s32>), %dst2:fpr(<2 x s32>) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.neon.ld2), %ptr(p0) :: (load (<2 x s64>))120 $d0 = COPY %dst1(<2 x s32>)121 $d1 = COPY %dst2(<2 x s32>)122 RET_ReallyLR implicit $d0, implicit $d1123...124---125name: LD2Twov4s126legalized: true127regBankSelected: true128tracksRegLiveness: true129body: |130 bb.0:131 liveins: $x0, $x1, $x2132 ; CHECK-LABEL: name: LD2Twov4s133 ; CHECK: liveins: $x0, $x1, $x2134 ; CHECK-NEXT: {{ $}}135 ; CHECK-NEXT: %ptr:gpr64sp = COPY $x0136 ; CHECK-NEXT: [[LD2Twov4s:%[0-9]+]]:qq = LD2Twov4s %ptr :: (load (<4 x s64>))137 ; CHECK-NEXT: %dst1:fpr128 = COPY [[LD2Twov4s]].qsub0138 ; CHECK-NEXT: %dst2:fpr128 = COPY [[LD2Twov4s]].qsub1139 ; CHECK-NEXT: $q0 = COPY %dst1140 ; CHECK-NEXT: $q1 = COPY %dst2141 ; CHECK-NEXT: RET_ReallyLR implicit $q0, implicit $q1142 %ptr:gpr(p0) = COPY $x0143 %dst1:fpr(<4 x s32>), %dst2:fpr(<4 x s32>) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.neon.ld2), %ptr(p0) :: (load (<4 x s64>))144 $q0 = COPY %dst1(<4 x s32>)145 $q1 = COPY %dst2(<4 x s32>)146 RET_ReallyLR implicit $q0, implicit $q1147...148---149name: LD2Twov2d_s64150legalized: true151regBankSelected: true152tracksRegLiveness: true153body: |154 bb.0:155 liveins: $x0, $x1, $x2156 ; CHECK-LABEL: name: LD2Twov2d_s64157 ; CHECK: liveins: $x0, $x1, $x2158 ; CHECK-NEXT: {{ $}}159 ; CHECK-NEXT: %ptr:gpr64sp = COPY $x0160 ; CHECK-NEXT: [[LD2Twov2d:%[0-9]+]]:qq = LD2Twov2d %ptr :: (load (<2 x s64>))161 ; CHECK-NEXT: %dst1:fpr128 = COPY [[LD2Twov2d]].qsub0162 ; CHECK-NEXT: %dst2:fpr128 = COPY [[LD2Twov2d]].qsub1163 ; CHECK-NEXT: $q0 = COPY %dst1164 ; CHECK-NEXT: $q1 = COPY %dst2165 ; CHECK-NEXT: RET_ReallyLR implicit $q0, implicit $q1166 %ptr:gpr(p0) = COPY $x0167 %dst1:fpr(<2 x s64>), %dst2:fpr(<2 x s64>) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.neon.ld2), %ptr(p0) :: (load (<2 x s64>))168 $q0 = COPY %dst1(<2 x s64>)169 $q1 = COPY %dst2(<2 x s64>)170 RET_ReallyLR implicit $q0, implicit $q1171...172---173name: LD2Twov2d_p0174legalized: true175regBankSelected: true176tracksRegLiveness: true177body: |178 bb.0:179 liveins: $x0, $x1, $x2180 ; CHECK-LABEL: name: LD2Twov2d_p0181 ; CHECK: liveins: $x0, $x1, $x2182 ; CHECK-NEXT: {{ $}}183 ; CHECK-NEXT: %ptr:gpr64sp = COPY $x0184 ; CHECK-NEXT: [[LD2Twov2d:%[0-9]+]]:qq = LD2Twov2d %ptr :: (load (<2 x p0>))185 ; CHECK-NEXT: %dst1:fpr128 = COPY [[LD2Twov2d]].qsub0186 ; CHECK-NEXT: %dst2:fpr128 = COPY [[LD2Twov2d]].qsub1187 ; CHECK-NEXT: $q0 = COPY %dst1188 ; CHECK-NEXT: $q1 = COPY %dst2189 ; CHECK-NEXT: RET_ReallyLR implicit $q0, implicit $q1190 %ptr:gpr(p0) = COPY $x0191 %dst1:fpr(<2 x p0>), %dst2:fpr(<2 x p0>) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.neon.ld2), %ptr(p0) :: (load (<2 x p0>))192 $q0 = COPY %dst1(<2 x p0>)193 $q1 = COPY %dst2(<2 x p0>)194 RET_ReallyLR implicit $q0, implicit $q1195...196---197name: LD1Twov1d_s64198legalized: true199regBankSelected: true200tracksRegLiveness: true201body: |202 bb.0:203 liveins: $x0, $x1, $x2204 ; CHECK-LABEL: name: LD1Twov1d_s64205 ; CHECK: liveins: $x0, $x1, $x2206 ; CHECK-NEXT: {{ $}}207 ; CHECK-NEXT: %ptr:gpr64sp = COPY $x0208 ; CHECK-NEXT: [[LD1Twov1d:%[0-9]+]]:dd = LD1Twov1d %ptr :: (load (s64))209 ; CHECK-NEXT: %dst1:fpr64 = COPY [[LD1Twov1d]].dsub0210 ; CHECK-NEXT: %dst2:fpr64 = COPY [[LD1Twov1d]].dsub1211 ; CHECK-NEXT: $d0 = COPY %dst1212 ; CHECK-NEXT: $d1 = COPY %dst2213 ; CHECK-NEXT: RET_ReallyLR implicit $d0, implicit $d1214 %ptr:gpr(p0) = COPY $x0215 %dst1:fpr(s64), %dst2:fpr(s64) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.neon.ld2), %ptr(p0) :: (load (s64))216 $d0 = COPY %dst1(s64)217 $d1 = COPY %dst2(s64)218 RET_ReallyLR implicit $d0, implicit $d1219...220---221name: LD1Twov1d_p0222legalized: true223regBankSelected: true224tracksRegLiveness: true225body: |226 bb.0:227 liveins: $x0, $x1, $x2228 ; CHECK-LABEL: name: LD1Twov1d_p0229 ; CHECK: liveins: $x0, $x1, $x2230 ; CHECK-NEXT: {{ $}}231 ; CHECK-NEXT: %ptr:gpr64sp = COPY $x0232 ; CHECK-NEXT: [[LD1Twov1d:%[0-9]+]]:dd = LD1Twov1d %ptr :: (load (p0))233 ; CHECK-NEXT: %dst1:fpr64 = COPY [[LD1Twov1d]].dsub0234 ; CHECK-NEXT: %dst2:fpr64 = COPY [[LD1Twov1d]].dsub1235 ; CHECK-NEXT: $d0 = COPY %dst1236 ; CHECK-NEXT: $d1 = COPY %dst2237 ; CHECK-NEXT: RET_ReallyLR implicit $d0, implicit $d1238 %ptr:gpr(p0) = COPY $x0239 %dst1:fpr(p0), %dst2:fpr(p0) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.neon.ld2), %ptr(p0) :: (load (p0))240 $d0 = COPY %dst1(p0)241 $d1 = COPY %dst2(p0)242 RET_ReallyLR implicit $d0, implicit $d1243