303 lines · plain
1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=aarch64 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s3...4---5name: LD4Fourv8b6legalized: true7regBankSelected: true8tracksRegLiveness: true9body: |10 bb.0:11 liveins: $x0, $x1, $x212 ; CHECK-LABEL: name: LD4Fourv8b13 ; CHECK: liveins: $x0, $x1, $x214 ; CHECK-NEXT: {{ $}}15 ; CHECK-NEXT: %ptr:gpr64sp = COPY $x016 ; CHECK-NEXT: [[LD4Fourv8b:%[0-9]+]]:dddd = LD4Fourv8b %ptr :: (load (<8 x s64>))17 ; CHECK-NEXT: %dst1:fpr64 = COPY [[LD4Fourv8b]].dsub018 ; CHECK-NEXT: %dst2:fpr64 = COPY [[LD4Fourv8b]].dsub119 ; CHECK-NEXT: %dst3:fpr64 = COPY [[LD4Fourv8b]].dsub220 ; CHECK-NEXT: %dst4:fpr64 = COPY [[LD4Fourv8b]].dsub321 ; CHECK-NEXT: $d0 = COPY %dst122 ; CHECK-NEXT: $d1 = COPY %dst223 ; CHECK-NEXT: $d2 = COPY %dst324 ; CHECK-NEXT: $d3 = COPY %dst425 ; CHECK-NEXT: RET_ReallyLR implicit $d0, implicit $d1, implicit $d2, implicit $d326 %ptr:gpr(p0) = COPY $x027 %dst1:fpr(<8 x s8>), %dst2:fpr(<8 x s8>), %dst3:fpr(<8 x s8>), %dst4:fpr(<8 x s8>)= G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.neon.ld4), %ptr(p0) :: (load (<8 x s64>))28 $d0 = COPY %dst1(<8 x s8>)29 $d1 = COPY %dst2(<8 x s8>)30 $d2 = COPY %dst3(<8 x s8>)31 $d3 = COPY %dst4(<8 x s8>)32 RET_ReallyLR implicit $d0, implicit $d1, implicit $d2, implicit $d333...34---35name: LD4Fourv16b36legalized: true37regBankSelected: true38tracksRegLiveness: true39body: |40 bb.0:41 liveins: $x0, $x1, $x242 ; CHECK-LABEL: name: LD4Fourv16b43 ; CHECK: liveins: $x0, $x1, $x244 ; CHECK-NEXT: {{ $}}45 ; CHECK-NEXT: %ptr:gpr64sp = COPY $x046 ; CHECK-NEXT: [[LD4Fourv16b:%[0-9]+]]:qqqq = LD4Fourv16b %ptr :: (load (<16 x s64>))47 ; CHECK-NEXT: %dst1:fpr128 = COPY [[LD4Fourv16b]].qsub048 ; CHECK-NEXT: %dst2:fpr128 = COPY [[LD4Fourv16b]].qsub149 ; CHECK-NEXT: %dst3:fpr128 = COPY [[LD4Fourv16b]].qsub250 ; CHECK-NEXT: %dst4:fpr128 = COPY [[LD4Fourv16b]].qsub351 ; CHECK-NEXT: $q0 = COPY %dst152 ; CHECK-NEXT: $q1 = COPY %dst253 ; CHECK-NEXT: $q2 = COPY %dst354 ; CHECK-NEXT: $q3 = COPY %dst455 ; CHECK-NEXT: RET_ReallyLR implicit $q0, implicit $q1, implicit $q2, implicit $q356 %ptr:gpr(p0) = COPY $x057 %dst1:fpr(<16 x s8>), %dst2:fpr(<16 x s8>), %dst3:fpr(<16 x s8>), %dst4:fpr(<16 x s8>) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.neon.ld4), %ptr(p0) :: (load (<16 x s64>))58 $q0 = COPY %dst1(<16 x s8>)59 $q1 = COPY %dst2(<16 x s8>)60 $q2 = COPY %dst3(<16 x s8>)61 $q3 = COPY %dst4(<16 x s8>)62 RET_ReallyLR implicit $q0, implicit $q1, implicit $q2, implicit $q363...64---65name: LD4Fourv4h66legalized: true67regBankSelected: true68tracksRegLiveness: true69body: |70 bb.0:71 liveins: $x072 ; CHECK-LABEL: name: LD4Fourv4h73 ; CHECK: liveins: $x074 ; CHECK-NEXT: {{ $}}75 ; CHECK-NEXT: %ptr:gpr64sp = COPY $x076 ; CHECK-NEXT: [[LD4Fourv4h:%[0-9]+]]:dddd = LD4Fourv4h %ptr :: (load (<4 x s64>))77 ; CHECK-NEXT: %dst1:fpr64 = COPY [[LD4Fourv4h]].dsub078 ; CHECK-NEXT: %dst2:fpr64 = COPY [[LD4Fourv4h]].dsub179 ; CHECK-NEXT: %dst3:fpr64 = COPY [[LD4Fourv4h]].dsub280 ; CHECK-NEXT: %dst4:fpr64 = COPY [[LD4Fourv4h]].dsub381 ; CHECK-NEXT: $d0 = COPY %dst182 ; CHECK-NEXT: $d1 = COPY %dst283 ; CHECK-NEXT: $d2 = COPY %dst384 ; CHECK-NEXT: $d3 = COPY %dst485 ; CHECK-NEXT: RET_ReallyLR implicit $d0, implicit $d1, implicit $d2, implicit $d386 %ptr:gpr(p0) = COPY $x087 %dst1:fpr(<4 x s16>), %dst2:fpr(<4 x s16>), %dst3:fpr(<4 x s16>), %dst4:fpr(<4 x s16>) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.neon.ld4), %ptr(p0) :: (load (<4 x s64>))88 $d0 = COPY %dst1(<4 x s16>)89 $d1 = COPY %dst2(<4 x s16>)90 $d2 = COPY %dst3(<4 x s16>)91 $d3 = COPY %dst4(<4 x s16>)92 RET_ReallyLR implicit $d0, implicit $d1, implicit $d2, implicit $d393...94---95name: LD4Fourv8h96legalized: true97regBankSelected: true98tracksRegLiveness: true99body: |100 bb.0:101 liveins: $x0, $x1, $x2102 ; CHECK-LABEL: name: LD4Fourv8h103 ; CHECK: liveins: $x0, $x1, $x2104 ; CHECK-NEXT: {{ $}}105 ; CHECK-NEXT: %ptr:gpr64sp = COPY $x0106 ; CHECK-NEXT: [[LD4Fourv8h:%[0-9]+]]:qqqq = LD4Fourv8h %ptr :: (load (<8 x s64>))107 ; CHECK-NEXT: %dst1:fpr128 = COPY [[LD4Fourv8h]].qsub0108 ; CHECK-NEXT: %dst2:fpr128 = COPY [[LD4Fourv8h]].qsub1109 ; CHECK-NEXT: %dst3:fpr128 = COPY [[LD4Fourv8h]].qsub2110 ; CHECK-NEXT: %dst4:fpr128 = COPY [[LD4Fourv8h]].qsub3111 ; CHECK-NEXT: $q0 = COPY %dst1112 ; CHECK-NEXT: $q1 = COPY %dst2113 ; CHECK-NEXT: $q2 = COPY %dst3114 ; CHECK-NEXT: $q3 = COPY %dst4115 ; CHECK-NEXT: RET_ReallyLR implicit $q0, implicit $q1, implicit $q2, implicit $q3116 %ptr:gpr(p0) = COPY $x0117 %dst1:fpr(<8 x s16>), %dst2:fpr(<8 x s16>), %dst3:fpr(<8 x s16>), %dst4:fpr(<8 x s16>) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.neon.ld4), %ptr(p0) :: (load (<8 x s64>))118 $q0 = COPY %dst1(<8 x s16>)119 $q1 = COPY %dst2(<8 x s16>)120 $q2 = COPY %dst3(<8 x s16>)121 $q3 = COPY %dst4(<8 x s16>)122 RET_ReallyLR implicit $q0, implicit $q1, implicit $q2, implicit $q3123...124---125name: LD4Fourv2s126legalized: true127regBankSelected: true128tracksRegLiveness: true129body: |130 bb.0:131 liveins: $x0, $x1, $x2132 ; CHECK-LABEL: name: LD4Fourv2s133 ; CHECK: liveins: $x0, $x1, $x2134 ; CHECK-NEXT: {{ $}}135 ; CHECK-NEXT: %ptr:gpr64sp = COPY $x0136 ; CHECK-NEXT: [[LD4Fourv2s:%[0-9]+]]:dddd = LD4Fourv2s %ptr :: (load (<2 x s64>))137 ; CHECK-NEXT: %dst1:fpr64 = COPY [[LD4Fourv2s]].dsub0138 ; CHECK-NEXT: %dst2:fpr64 = COPY [[LD4Fourv2s]].dsub1139 ; CHECK-NEXT: %dst3:fpr64 = COPY [[LD4Fourv2s]].dsub2140 ; CHECK-NEXT: %dst4:fpr64 = COPY [[LD4Fourv2s]].dsub3141 ; CHECK-NEXT: $d0 = COPY %dst1142 ; CHECK-NEXT: $d1 = COPY %dst2143 ; CHECK-NEXT: $d2 = COPY %dst3144 ; CHECK-NEXT: $d3 = COPY %dst4145 ; CHECK-NEXT: RET_ReallyLR implicit $d0, implicit $d1, implicit $d2, implicit $d3146 %ptr:gpr(p0) = COPY $x0147 %dst1:fpr(<2 x s32>), %dst2:fpr(<2 x s32>), %dst3:fpr(<2 x s32>), %dst4:fpr(<2 x s32>) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.neon.ld4), %ptr(p0) :: (load (<2 x s64>))148 $d0 = COPY %dst1(<2 x s32>)149 $d1 = COPY %dst2(<2 x s32>)150 $d2 = COPY %dst3(<2 x s32>)151 $d3 = COPY %dst4(<2 x s32>)152 RET_ReallyLR implicit $d0, implicit $d1, implicit $d2, implicit $d3153...154---155name: LD4Fourv4s156legalized: true157regBankSelected: true158tracksRegLiveness: true159body: |160 bb.0:161 liveins: $x0, $x1, $x2162 ; CHECK-LABEL: name: LD4Fourv4s163 ; CHECK: liveins: $x0, $x1, $x2164 ; CHECK-NEXT: {{ $}}165 ; CHECK-NEXT: %ptr:gpr64sp = COPY $x0166 ; CHECK-NEXT: [[LD4Fourv4s:%[0-9]+]]:qqqq = LD4Fourv4s %ptr :: (load (<4 x s64>))167 ; CHECK-NEXT: %dst1:fpr128 = COPY [[LD4Fourv4s]].qsub0168 ; CHECK-NEXT: %dst2:fpr128 = COPY [[LD4Fourv4s]].qsub1169 ; CHECK-NEXT: %dst3:fpr128 = COPY [[LD4Fourv4s]].qsub2170 ; CHECK-NEXT: %dst4:fpr128 = COPY [[LD4Fourv4s]].qsub3171 ; CHECK-NEXT: $q0 = COPY %dst1172 ; CHECK-NEXT: $q1 = COPY %dst2173 ; CHECK-NEXT: $q2 = COPY %dst3174 ; CHECK-NEXT: $q3 = COPY %dst4175 ; CHECK-NEXT: RET_ReallyLR implicit $q0, implicit $q1, implicit $q2, implicit $q3176 %ptr:gpr(p0) = COPY $x0177 %dst1:fpr(<4 x s32>), %dst2:fpr(<4 x s32>), %dst3:fpr(<4 x s32>), %dst4:fpr(<4 x s32>)= G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.neon.ld4), %ptr(p0) :: (load (<4 x s64>))178 $q0 = COPY %dst1(<4 x s32>)179 $q1 = COPY %dst2(<4 x s32>)180 $q2 = COPY %dst3(<4 x s32>)181 $q3 = COPY %dst4(<4 x s32>)182 RET_ReallyLR implicit $q0, implicit $q1, implicit $q2, implicit $q3183...184---185name: LD4Fourv2d_v2s64186legalized: true187regBankSelected: true188tracksRegLiveness: true189body: |190 bb.0:191 liveins: $x0, $x1, $x2192 ; CHECK-LABEL: name: LD4Fourv2d_v2s64193 ; CHECK: liveins: $x0, $x1, $x2194 ; CHECK-NEXT: {{ $}}195 ; CHECK-NEXT: %ptr:gpr64sp = COPY $x0196 ; CHECK-NEXT: [[LD4Fourv2d:%[0-9]+]]:qqqq = LD4Fourv2d %ptr :: (load (<2 x s64>))197 ; CHECK-NEXT: %dst1:fpr128 = COPY [[LD4Fourv2d]].qsub0198 ; CHECK-NEXT: %dst2:fpr128 = COPY [[LD4Fourv2d]].qsub1199 ; CHECK-NEXT: %dst3:fpr128 = COPY [[LD4Fourv2d]].qsub2200 ; CHECK-NEXT: %dst4:fpr128 = COPY [[LD4Fourv2d]].qsub3201 ; CHECK-NEXT: $q0 = COPY %dst1202 ; CHECK-NEXT: $q1 = COPY %dst2203 ; CHECK-NEXT: $q2 = COPY %dst3204 ; CHECK-NEXT: $q3 = COPY %dst4205 ; CHECK-NEXT: RET_ReallyLR implicit $q0, implicit $q1, implicit $q2, implicit $q3206 %ptr:gpr(p0) = COPY $x0207 %dst1:fpr(<2 x s64>), %dst2:fpr(<2 x s64>), %dst3:fpr(<2 x s64>), %dst4:fpr(<2 x s64>) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.neon.ld4), %ptr(p0) :: (load (<2 x s64>))208 $q0 = COPY %dst1(<2 x s64>)209 $q1 = COPY %dst2(<2 x s64>)210 $q2 = COPY %dst3(<2 x s64>)211 $q3 = COPY %dst4(<2 x s64>)212 RET_ReallyLR implicit $q0, implicit $q1, implicit $q2, implicit $q3213...214---215name: LD4Fourv2d_v2p0216legalized: true217regBankSelected: true218tracksRegLiveness: true219body: |220 bb.0:221 liveins: $x0, $x1, $x2222 ; CHECK-LABEL: name: LD4Fourv2d_v2p0223 ; CHECK: liveins: $x0, $x1, $x2224 ; CHECK-NEXT: {{ $}}225 ; CHECK-NEXT: %ptr:gpr64sp = COPY $x0226 ; CHECK-NEXT: [[LD4Fourv2d:%[0-9]+]]:qqqq = LD4Fourv2d %ptr :: (load (<2 x p0>))227 ; CHECK-NEXT: %dst1:fpr128 = COPY [[LD4Fourv2d]].qsub0228 ; CHECK-NEXT: %dst2:fpr128 = COPY [[LD4Fourv2d]].qsub1229 ; CHECK-NEXT: %dst3:fpr128 = COPY [[LD4Fourv2d]].qsub2230 ; CHECK-NEXT: %dst4:fpr128 = COPY [[LD4Fourv2d]].qsub3231 ; CHECK-NEXT: $q0 = COPY %dst1232 ; CHECK-NEXT: $q1 = COPY %dst2233 ; CHECK-NEXT: $q2 = COPY %dst3234 ; CHECK-NEXT: $q3 = COPY %dst4235 ; CHECK-NEXT: RET_ReallyLR implicit $q0, implicit $q1, implicit $q2, implicit $q3236 %ptr:gpr(p0) = COPY $x0237 %dst1:fpr(<2 x p0>), %dst2:fpr(<2 x p0>), %dst3:fpr(<2 x p0>), %dst4:fpr(<2 x p0>) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.neon.ld4), %ptr(p0) :: (load (<2 x p0>))238 $q0 = COPY %dst1(<2 x p0>)239 $q1 = COPY %dst2(<2 x p0>)240 $q2 = COPY %dst3(<2 x p0>)241 $q3 = COPY %dst4(<2 x p0>)242 RET_ReallyLR implicit $q0, implicit $q1, implicit $q2, implicit $q3243...244---245name: LD1Fourv1d_s64246legalized: true247regBankSelected: true248tracksRegLiveness: true249body: |250 bb.0:251 liveins: $x0, $x1, $x2252 ; CHECK-LABEL: name: LD1Fourv1d_s64253 ; CHECK: liveins: $x0, $x1, $x2254 ; CHECK-NEXT: {{ $}}255 ; CHECK-NEXT: %ptr:gpr64sp = COPY $x0256 ; CHECK-NEXT: [[LD1Fourv1d:%[0-9]+]]:dddd = LD1Fourv1d %ptr :: (load (s64))257 ; CHECK-NEXT: %dst1:fpr64 = COPY [[LD1Fourv1d]].dsub0258 ; CHECK-NEXT: %dst2:fpr64 = COPY [[LD1Fourv1d]].dsub1259 ; CHECK-NEXT: %dst3:fpr64 = COPY [[LD1Fourv1d]].dsub2260 ; CHECK-NEXT: %dst4:fpr64 = COPY [[LD1Fourv1d]].dsub3261 ; CHECK-NEXT: $d0 = COPY %dst1262 ; CHECK-NEXT: $d1 = COPY %dst2263 ; CHECK-NEXT: $d2 = COPY %dst3264 ; CHECK-NEXT: $d3 = COPY %dst4265 ; CHECK-NEXT: RET_ReallyLR implicit $d0, implicit $d1, implicit $d2, implicit $d3266 %ptr:gpr(p0) = COPY $x0267 %dst1:fpr(s64), %dst2:fpr(s64), %dst3:fpr(s64), %dst4:fpr(s64) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.neon.ld4), %ptr(p0) :: (load (s64))268 $d0 = COPY %dst1(s64)269 $d1 = COPY %dst2(s64)270 $d2 = COPY %dst3(s64)271 $d3 = COPY %dst4(s64)272 RET_ReallyLR implicit $d0, implicit $d1, implicit $d2, implicit $d3273...274---275name: LD1Fourv1d_p0276legalized: true277regBankSelected: true278tracksRegLiveness: true279body: |280 bb.0:281 liveins: $x0, $x1, $x2282 ; CHECK-LABEL: name: LD1Fourv1d_p0283 ; CHECK: liveins: $x0, $x1, $x2284 ; CHECK-NEXT: {{ $}}285 ; CHECK-NEXT: %ptr:gpr64sp = COPY $x0286 ; CHECK-NEXT: [[LD1Fourv1d:%[0-9]+]]:dddd = LD1Fourv1d %ptr :: (load (p0))287 ; CHECK-NEXT: %dst1:fpr64 = COPY [[LD1Fourv1d]].dsub0288 ; CHECK-NEXT: %dst2:fpr64 = COPY [[LD1Fourv1d]].dsub1289 ; CHECK-NEXT: %dst3:fpr64 = COPY [[LD1Fourv1d]].dsub2290 ; CHECK-NEXT: %dst4:fpr64 = COPY [[LD1Fourv1d]].dsub3291 ; CHECK-NEXT: $d0 = COPY %dst1292 ; CHECK-NEXT: $d1 = COPY %dst2293 ; CHECK-NEXT: $d2 = COPY %dst3294 ; CHECK-NEXT: $d3 = COPY %dst4295 ; CHECK-NEXT: RET_ReallyLR implicit $d0, implicit $d1, implicit $d2, implicit $d3296 %ptr:gpr(p0) = COPY $x0297 %dst1:fpr(p0), %dst2:fpr(p0), %dst3:fpr(p0), %dst4:fpr(p0) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.neon.ld4), %ptr(p0) :: (load (p0))298 $d0 = COPY %dst1(p0)299 $d1 = COPY %dst2(p0)300 $d2 = COPY %dst3(p0)301 $d3 = COPY %dst4(p0)302 RET_ReallyLR implicit $d0, implicit $d1, implicit $d2, implicit $d3303