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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=aarch64-unknown-unknown -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s3 4--- |5 define void @test_load_acquire_i8(ptr %addr) { ret void }6 define void @test_load_acquire_i16(ptr %addr) { ret void }7 define void @test_load_acquire_i32(ptr %addr) { ret void }8 define void @test_load_acquire_i64(ptr %addr) { ret void }9...10---11 12name: test_load_acquire_i813alignment: 414legalized: true15regBankSelected: true16tracksRegLiveness: true17body: |18 bb.0:19 liveins: $x020 ; CHECK-LABEL: name: test_load_acquire_i821 ; CHECK: liveins: $x022 ; CHECK-NEXT: {{ $}}23 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x024 ; CHECK-NEXT: [[LDAXRB:%[0-9]+]]:gpr32 = LDAXRB [[COPY]] :: (volatile load (s8) from %ir.addr)25 ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64all = SUBREG_TO_REG 0, [[LDAXRB]], %subreg.sub_3226 ; CHECK-NEXT: $x1 = COPY [[SUBREG_TO_REG]]27 ; CHECK-NEXT: RET_ReallyLR implicit $x128 %0:gpr(p0) = COPY $x029 %1:gpr(s64) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.ldaxr), %0(p0) :: (volatile load (s8) from %ir.addr)30 $x1 = COPY %131 RET_ReallyLR implicit $x132 33...34---35name: test_load_acquire_i1636alignment: 437legalized: true38regBankSelected: true39tracksRegLiveness: true40body: |41 bb.0:42 liveins: $x043 ; CHECK-LABEL: name: test_load_acquire_i1644 ; CHECK: liveins: $x045 ; CHECK-NEXT: {{ $}}46 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x047 ; CHECK-NEXT: [[LDAXRH:%[0-9]+]]:gpr32 = LDAXRH [[COPY]] :: (volatile load (s16) from %ir.addr)48 ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64all = SUBREG_TO_REG 0, [[LDAXRH]], %subreg.sub_3249 ; CHECK-NEXT: $x1 = COPY [[SUBREG_TO_REG]]50 ; CHECK-NEXT: RET_ReallyLR implicit $x151 %0:gpr(p0) = COPY $x052 %1:gpr(s64) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.ldaxr), %0(p0) :: (volatile load (s16) from %ir.addr)53 $x1 = COPY %154 RET_ReallyLR implicit $x155 56...57---58name: test_load_acquire_i3259alignment: 460legalized: true61regBankSelected: true62tracksRegLiveness: true63body: |64 bb.0:65 liveins: $x066 ; CHECK-LABEL: name: test_load_acquire_i3267 ; CHECK: liveins: $x068 ; CHECK-NEXT: {{ $}}69 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x070 ; CHECK-NEXT: [[LDAXRW:%[0-9]+]]:gpr32 = LDAXRW [[COPY]] :: (volatile load (s32) from %ir.addr)71 ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64all = SUBREG_TO_REG 0, [[LDAXRW]], %subreg.sub_3272 ; CHECK-NEXT: $x1 = COPY [[SUBREG_TO_REG]]73 ; CHECK-NEXT: RET_ReallyLR implicit $x174 %0:gpr(p0) = COPY $x075 %1:gpr(s64) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.ldaxr), %0(p0) :: (volatile load (s32) from %ir.addr)76 $x1 = COPY %177 RET_ReallyLR implicit $x178 79...80---81name: test_load_acquire_i6482alignment: 483legalized: true84regBankSelected: true85tracksRegLiveness: true86body: |87 bb.0:88 liveins: $x089 ; CHECK-LABEL: name: test_load_acquire_i6490 ; CHECK: liveins: $x091 ; CHECK-NEXT: {{ $}}92 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x093 ; CHECK-NEXT: [[LDAXRX:%[0-9]+]]:gpr64 = LDAXRX [[COPY]] :: (volatile load (s64) from %ir.addr)94 ; CHECK-NEXT: $x1 = COPY [[LDAXRX]]95 ; CHECK-NEXT: RET_ReallyLR implicit $x196 %0:gpr(p0) = COPY $x097 %1:gpr(s64) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.ldaxr), %0(p0) :: (volatile load (s64) from %ir.addr)98 $x1 = COPY %199 RET_ReallyLR implicit $x1100