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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=aarch64-unknown-unknown -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s3 4--- |5 define void @test_load_i8(ptr %addr) { ret void }6 define void @test_load_i16(ptr %addr) { ret void }7 define void @test_load_i32(ptr %addr) { ret void }8 define void @test_load_i64(ptr %addr) { ret void }9...10---11name: test_load_i812alignment: 413legalized: true14regBankSelected: true15tracksRegLiveness: true16body: |17 bb.0:18 liveins: $x019 ; CHECK-LABEL: name: test_load_i820 ; CHECK: liveins: $x021 ; CHECK-NEXT: {{ $}}22 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x023 ; CHECK-NEXT: [[LDXRB:%[0-9]+]]:gpr32 = LDXRB [[COPY]] :: (volatile load (s8) from %ir.addr)24 ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64all = SUBREG_TO_REG 0, [[LDXRB]], %subreg.sub_3225 ; CHECK-NEXT: $x1 = COPY [[SUBREG_TO_REG]]26 ; CHECK-NEXT: RET_ReallyLR implicit $x127 %0:gpr(p0) = COPY $x028 %1:gpr(s64) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.ldxr), %0(p0) :: (volatile load (s8) from %ir.addr)29 $x1 = COPY %1(s64)30 RET_ReallyLR implicit $x131 32...33---34name: test_load_i1635alignment: 436legalized: true37regBankSelected: true38tracksRegLiveness: true39body: |40 bb.0:41 liveins: $x042 ; CHECK-LABEL: name: test_load_i1643 ; CHECK: liveins: $x044 ; CHECK-NEXT: {{ $}}45 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x046 ; CHECK-NEXT: [[LDXRH:%[0-9]+]]:gpr32 = LDXRH [[COPY]] :: (volatile load (s16) from %ir.addr)47 ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64all = SUBREG_TO_REG 0, [[LDXRH]], %subreg.sub_3248 ; CHECK-NEXT: $x1 = COPY [[SUBREG_TO_REG]]49 ; CHECK-NEXT: RET_ReallyLR implicit $x150 %0:gpr(p0) = COPY $x051 %1:gpr(s64) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.ldxr), %0(p0) :: (volatile load (s16) from %ir.addr)52 $x1 = COPY %1(s64)53 RET_ReallyLR implicit $x154 55...56---57name: test_load_i3258alignment: 459legalized: true60regBankSelected: true61tracksRegLiveness: true62body: |63 bb.0:64 liveins: $x065 ; CHECK-LABEL: name: test_load_i3266 ; CHECK: liveins: $x067 ; CHECK-NEXT: {{ $}}68 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x069 ; CHECK-NEXT: [[LDXRW:%[0-9]+]]:gpr32 = LDXRW [[COPY]] :: (volatile load (s32) from %ir.addr)70 ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64all = SUBREG_TO_REG 0, [[LDXRW]], %subreg.sub_3271 ; CHECK-NEXT: $x1 = COPY [[SUBREG_TO_REG]]72 ; CHECK-NEXT: RET_ReallyLR implicit $x173 %0:gpr(p0) = COPY $x074 %1:gpr(s64) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.ldxr), %0(p0) :: (volatile load (s32) from %ir.addr)75 $x1 = COPY %1(s64)76 RET_ReallyLR implicit $x177 78 79...80---81name: test_load_i6482alignment: 483legalized: true84regBankSelected: true85tracksRegLiveness: true86body: |87 bb.0:88 liveins: $x089 ; CHECK-LABEL: name: test_load_i6490 ; CHECK: liveins: $x091 ; CHECK-NEXT: {{ $}}92 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x093 ; CHECK-NEXT: [[LDXRX:%[0-9]+]]:gpr64 = LDXRX [[COPY]] :: (volatile load (s64) from %ir.addr)94 ; CHECK-NEXT: $x1 = COPY [[LDXRX]]95 ; CHECK-NEXT: RET_ReallyLR implicit $x196 %0:gpr(p0) = COPY $x097 %1:gpr(s64) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.ldxr), %0(p0) :: (volatile load (s64) from %ir.addr)98 $x1 = COPY %1(s64)99 RET_ReallyLR implicit $x1100