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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s3 4--- |5 target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"6 7 define void @load_s64_gpr(ptr %addr) { ret void }8 define void @load_s32_gpr(ptr %addr) { ret void }9 define void @load_s16_gpr_anyext(ptr %addr) { ret void }10 define void @load_s16_gpr(ptr %addr) { ret void }11 define void @load_s8_gpr_anyext(ptr %addr) { ret void }12 define void @load_s8_gpr(ptr %addr) { ret void }13 14 define void @load_fi_s64_gpr() {15 %ptr0 = alloca i6416 ret void17 }18 19 define void @load_gep_128_s64_gpr(ptr %addr) { ret void }20 define void @load_gep_512_s32_gpr(ptr %addr) { ret void }21 define void @load_gep_64_s16_gpr(ptr %addr) { ret void }22 define void @load_gep_1_s8_gpr(ptr %addr) { ret void }23 24 define void @load_s64_fpr(ptr %addr) { ret void }25 define void @load_s32_fpr(ptr %addr) { ret void }26 define void @load_s16_fpr(ptr %addr) { ret void }27 define void @load_s8_fpr(ptr %addr) { ret void }28 29 define void @load_gep_8_s64_fpr(ptr %addr) { ret void }30 define void @load_gep_16_s32_fpr(ptr %addr) { ret void }31 define void @load_gep_64_s16_fpr(ptr %addr) { ret void }32 define void @load_gep_32_s8_fpr(ptr %addr) { ret void }33 34 define void @load_v2s32(ptr %addr) { ret void }35 define void @load_v2s64(ptr %addr) { ret void }36 37 define void @load_4xi16(ptr %ptr) { ret void }38 define void @load_4xi32(ptr %ptr) { ret void }39 define void @load_8xi16(ptr %ptr) { ret void }40 define void @load_16xi8(ptr %ptr) { ret void }41 define void @anyext_on_fpr() { ret void }42 define void @anyext_on_fpr8() { ret void }43 44 define void @load_s32_gpr_LD1() { ret void }45 define void @load_s32_gpr_GIM() { ret void }46 47...48---49name: load_s64_gpr50legalized: true51regBankSelected: true52 53registers:54 - { id: 0, class: gpr }55 - { id: 1, class: gpr }56 57body: |58 bb.0:59 liveins: $x060 61 ; CHECK-LABEL: name: load_s64_gpr62 ; CHECK: liveins: $x063 ; CHECK-NEXT: {{ $}}64 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x065 ; CHECK-NEXT: [[LDRXui:%[0-9]+]]:gpr64 = LDRXui [[COPY]], 0 :: (load (s64) from %ir.addr)66 ; CHECK-NEXT: $x0 = COPY [[LDRXui]]67 %0(p0) = COPY $x068 %1(s64) = G_LOAD %0 :: (load (s64) from %ir.addr)69 $x0 = COPY %1(s64)70...71 72---73name: load_s32_gpr74legalized: true75regBankSelected: true76 77registers:78 - { id: 0, class: gpr }79 - { id: 1, class: gpr }80 81body: |82 bb.0:83 liveins: $x084 85 ; CHECK-LABEL: name: load_s32_gpr86 ; CHECK: liveins: $x087 ; CHECK-NEXT: {{ $}}88 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x089 ; CHECK-NEXT: [[LDRWui:%[0-9]+]]:gpr32 = LDRWui [[COPY]], 0 :: (load (s32) from %ir.addr)90 ; CHECK-NEXT: $w0 = COPY [[LDRWui]]91 %0(p0) = COPY $x092 %1(s32) = G_LOAD %0 :: (load (s32) from %ir.addr)93 $w0 = COPY %1(s32)94...95 96---97name: load_s16_gpr_anyext98legalized: true99regBankSelected: true100 101body: |102 bb.0:103 liveins: $x0104 105 ; CHECK-LABEL: name: load_s16_gpr_anyext106 ; CHECK: liveins: $x0107 ; CHECK-NEXT: {{ $}}108 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0109 ; CHECK-NEXT: [[LDRHHui:%[0-9]+]]:gpr32 = LDRHHui [[COPY]], 0 :: (load (s16) from %ir.addr)110 ; CHECK-NEXT: $w0 = COPY [[LDRHHui]]111 %0:gpr(p0) = COPY $x0112 %1:gpr(s32) = G_LOAD %0 :: (load (s16) from %ir.addr)113 $w0 = COPY %1(s32)114...115 116---117name: load_s16_gpr118legalized: true119regBankSelected: true120 121registers:122 - { id: 0, class: gpr }123 - { id: 1, class: gpr }124 125body: |126 bb.0:127 liveins: $x0128 129 ; CHECK-LABEL: name: load_s16_gpr130 ; CHECK: liveins: $x0131 ; CHECK-NEXT: {{ $}}132 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0133 ; CHECK-NEXT: [[LDRHHui:%[0-9]+]]:gpr32 = LDRHHui [[COPY]], 0 :: (load (s16) from %ir.addr)134 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32all = COPY [[LDRHHui]]135 ; CHECK-NEXT: $w0 = COPY [[COPY1]]136 %0(p0) = COPY $x0137 %1(s16) = G_LOAD %0 :: (load (s16) from %ir.addr)138 %2:gpr(s32) = G_ANYEXT %1139 $w0 = COPY %2(s32)140...141 142---143name: load_s8_gpr_anyext144legalized: true145regBankSelected: true146 147body: |148 bb.0:149 liveins: $x0150 151 ; CHECK-LABEL: name: load_s8_gpr_anyext152 ; CHECK: liveins: $x0153 ; CHECK-NEXT: {{ $}}154 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0155 ; CHECK-NEXT: [[LDRBBui:%[0-9]+]]:gpr32 = LDRBBui [[COPY]], 0 :: (load (s8) from %ir.addr)156 ; CHECK-NEXT: $w0 = COPY [[LDRBBui]]157 %0:gpr(p0) = COPY $x0158 %1:gpr(s32) = G_LOAD %0 :: (load (s8) from %ir.addr)159 $w0 = COPY %1(s32)160...161 162---163name: load_s8_gpr164legalized: true165regBankSelected: true166 167registers:168 - { id: 0, class: gpr }169 - { id: 1, class: gpr }170 171body: |172 bb.0:173 liveins: $x0174 175 ; CHECK-LABEL: name: load_s8_gpr176 ; CHECK: liveins: $x0177 ; CHECK-NEXT: {{ $}}178 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0179 ; CHECK-NEXT: [[LDRBBui:%[0-9]+]]:gpr32 = LDRBBui [[COPY]], 0 :: (load (s8) from %ir.addr)180 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32all = COPY [[LDRBBui]]181 ; CHECK-NEXT: $w0 = COPY [[COPY1]]182 %0(p0) = COPY $x0183 %1(s8) = G_LOAD %0 :: (load (s8) from %ir.addr)184 %2:gpr(s32) = G_ANYEXT %1185 $w0 = COPY %2(s32)186...187 188---189name: load_fi_s64_gpr190legalized: true191regBankSelected: true192 193registers:194 - { id: 0, class: gpr }195 - { id: 1, class: gpr }196 197stack:198 - { id: 0, name: ptr0, offset: 0, size: 8, alignment: 8 }199 200body: |201 bb.0:202 liveins: $x0203 204 ; CHECK-LABEL: name: load_fi_s64_gpr205 ; CHECK: liveins: $x0206 ; CHECK-NEXT: {{ $}}207 ; CHECK-NEXT: [[LDRXui:%[0-9]+]]:gpr64 = LDRXui %stack.0.ptr0, 0 :: (load (s64))208 ; CHECK-NEXT: $x0 = COPY [[LDRXui]]209 %0(p0) = G_FRAME_INDEX %stack.0.ptr0210 %1(s64) = G_LOAD %0 :: (load (s64))211 $x0 = COPY %1(s64)212...213 214---215name: load_gep_128_s64_gpr216legalized: true217regBankSelected: true218 219registers:220 - { id: 0, class: gpr }221 - { id: 1, class: gpr }222 - { id: 2, class: gpr }223 - { id: 3, class: gpr }224 225body: |226 bb.0:227 liveins: $x0228 229 ; CHECK-LABEL: name: load_gep_128_s64_gpr230 ; CHECK: liveins: $x0231 ; CHECK-NEXT: {{ $}}232 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0233 ; CHECK-NEXT: [[LDRXui:%[0-9]+]]:gpr64 = LDRXui [[COPY]], 16 :: (load (s64) from %ir.addr)234 ; CHECK-NEXT: $x0 = COPY [[LDRXui]]235 %0(p0) = COPY $x0236 %1(s64) = G_CONSTANT i64 128237 %2(p0) = G_PTR_ADD %0, %1238 %3(s64) = G_LOAD %2 :: (load (s64) from %ir.addr)239 $x0 = COPY %3240...241 242---243name: load_gep_512_s32_gpr244legalized: true245regBankSelected: true246 247registers:248 - { id: 0, class: gpr }249 - { id: 1, class: gpr }250 - { id: 2, class: gpr }251 - { id: 3, class: gpr }252 253body: |254 bb.0:255 liveins: $x0256 257 ; CHECK-LABEL: name: load_gep_512_s32_gpr258 ; CHECK: liveins: $x0259 ; CHECK-NEXT: {{ $}}260 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0261 ; CHECK-NEXT: [[LDRWui:%[0-9]+]]:gpr32 = LDRWui [[COPY]], 128 :: (load (s32) from %ir.addr)262 ; CHECK-NEXT: $w0 = COPY [[LDRWui]]263 %0(p0) = COPY $x0264 %1(s64) = G_CONSTANT i64 512265 %2(p0) = G_PTR_ADD %0, %1266 %3(s32) = G_LOAD %2 :: (load (s32) from %ir.addr)267 $w0 = COPY %3268...269 270---271name: load_gep_64_s16_gpr272legalized: true273regBankSelected: true274 275registers:276 - { id: 0, class: gpr }277 - { id: 1, class: gpr }278 - { id: 2, class: gpr }279 - { id: 3, class: gpr }280 281body: |282 bb.0:283 liveins: $x0284 285 ; CHECK-LABEL: name: load_gep_64_s16_gpr286 ; CHECK: liveins: $x0287 ; CHECK-NEXT: {{ $}}288 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0289 ; CHECK-NEXT: [[LDRHHui:%[0-9]+]]:gpr32 = LDRHHui [[COPY]], 32 :: (load (s16) from %ir.addr)290 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32all = COPY [[LDRHHui]]291 ; CHECK-NEXT: $w0 = COPY [[COPY1]]292 %0(p0) = COPY $x0293 %1(s64) = G_CONSTANT i64 64294 %2(p0) = G_PTR_ADD %0, %1295 %3(s16) = G_LOAD %2 :: (load (s16) from %ir.addr)296 %4:gpr(s32) = G_ANYEXT %3297 $w0 = COPY %4298...299 300---301name: load_gep_1_s8_gpr302legalized: true303regBankSelected: true304 305registers:306 - { id: 0, class: gpr }307 - { id: 1, class: gpr }308 - { id: 2, class: gpr }309 - { id: 3, class: gpr }310 311body: |312 bb.0:313 liveins: $x0314 315 ; CHECK-LABEL: name: load_gep_1_s8_gpr316 ; CHECK: liveins: $x0317 ; CHECK-NEXT: {{ $}}318 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0319 ; CHECK-NEXT: [[LDRBBui:%[0-9]+]]:gpr32 = LDRBBui [[COPY]], 1 :: (load (s8) from %ir.addr)320 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32all = COPY [[LDRBBui]]321 ; CHECK-NEXT: $w0 = COPY [[COPY1]]322 %0(p0) = COPY $x0323 %1(s64) = G_CONSTANT i64 1324 %2(p0) = G_PTR_ADD %0, %1325 %3(s8) = G_LOAD %2 :: (load (s8) from %ir.addr)326 %4:gpr(s32) = G_ANYEXT %3327 $w0 = COPY %4328...329 330---331name: load_s64_fpr332legalized: true333regBankSelected: true334 335registers:336 - { id: 0, class: gpr }337 - { id: 1, class: fpr }338 339body: |340 bb.0:341 liveins: $x0342 343 ; CHECK-LABEL: name: load_s64_fpr344 ; CHECK: liveins: $x0345 ; CHECK-NEXT: {{ $}}346 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0347 ; CHECK-NEXT: [[LDRDui:%[0-9]+]]:fpr64 = LDRDui [[COPY]], 0 :: (load (s64) from %ir.addr)348 ; CHECK-NEXT: $d0 = COPY [[LDRDui]]349 %0(p0) = COPY $x0350 %1(s64) = G_LOAD %0 :: (load (s64) from %ir.addr)351 $d0 = COPY %1(s64)352...353 354---355name: load_s32_fpr356legalized: true357regBankSelected: true358 359registers:360 - { id: 0, class: gpr }361 - { id: 1, class: fpr }362 363body: |364 bb.0:365 liveins: $x0366 367 ; CHECK-LABEL: name: load_s32_fpr368 ; CHECK: liveins: $x0369 ; CHECK-NEXT: {{ $}}370 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0371 ; CHECK-NEXT: [[LDRSui:%[0-9]+]]:fpr32 = LDRSui [[COPY]], 0 :: (load (s32) from %ir.addr)372 ; CHECK-NEXT: $s0 = COPY [[LDRSui]]373 %0(p0) = COPY $x0374 %1(s32) = G_LOAD %0 :: (load (s32) from %ir.addr)375 $s0 = COPY %1(s32)376...377 378---379name: load_s16_fpr380legalized: true381regBankSelected: true382 383registers:384 - { id: 0, class: gpr }385 - { id: 1, class: fpr }386 387body: |388 bb.0:389 liveins: $x0390 391 ; CHECK-LABEL: name: load_s16_fpr392 ; CHECK: liveins: $x0393 ; CHECK-NEXT: {{ $}}394 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0395 ; CHECK-NEXT: [[LDRHui:%[0-9]+]]:fpr16 = LDRHui [[COPY]], 0 :: (load (s16) from %ir.addr)396 ; CHECK-NEXT: $h0 = COPY [[LDRHui]]397 %0(p0) = COPY $x0398 %1(s16) = G_LOAD %0 :: (load (s16) from %ir.addr)399 $h0 = COPY %1(s16)400...401 402---403name: load_s8_fpr404legalized: true405regBankSelected: true406 407registers:408 - { id: 0, class: gpr }409 - { id: 1, class: fpr }410 411body: |412 bb.0:413 liveins: $x0414 415 ; CHECK-LABEL: name: load_s8_fpr416 ; CHECK: liveins: $x0417 ; CHECK-NEXT: {{ $}}418 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0419 ; CHECK-NEXT: [[LDRBui:%[0-9]+]]:fpr8 = LDRBui [[COPY]], 0 :: (load (s8) from %ir.addr)420 ; CHECK-NEXT: $b0 = COPY [[LDRBui]]421 %0(p0) = COPY $x0422 %1(s8) = G_LOAD %0 :: (load (s8) from %ir.addr)423 $b0 = COPY %1(s8)424...425 426---427name: load_gep_8_s64_fpr428legalized: true429regBankSelected: true430 431registers:432 - { id: 0, class: gpr }433 - { id: 1, class: gpr }434 - { id: 2, class: gpr }435 - { id: 3, class: fpr }436 437body: |438 bb.0:439 liveins: $x0440 441 ; CHECK-LABEL: name: load_gep_8_s64_fpr442 ; CHECK: liveins: $x0443 ; CHECK-NEXT: {{ $}}444 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0445 ; CHECK-NEXT: [[LDRDui:%[0-9]+]]:fpr64 = LDRDui [[COPY]], 1 :: (load (s64) from %ir.addr)446 ; CHECK-NEXT: $d0 = COPY [[LDRDui]]447 %0(p0) = COPY $x0448 %1(s64) = G_CONSTANT i64 8449 %2(p0) = G_PTR_ADD %0, %1450 %3(s64) = G_LOAD %2 :: (load (s64) from %ir.addr)451 $d0 = COPY %3452...453 454---455name: load_gep_16_s32_fpr456legalized: true457regBankSelected: true458 459registers:460 - { id: 0, class: gpr }461 - { id: 1, class: gpr }462 - { id: 2, class: gpr }463 - { id: 3, class: fpr }464 465body: |466 bb.0:467 liveins: $x0468 469 ; CHECK-LABEL: name: load_gep_16_s32_fpr470 ; CHECK: liveins: $x0471 ; CHECK-NEXT: {{ $}}472 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0473 ; CHECK-NEXT: [[LDRSui:%[0-9]+]]:fpr32 = LDRSui [[COPY]], 4 :: (load (s32) from %ir.addr)474 ; CHECK-NEXT: $s0 = COPY [[LDRSui]]475 %0(p0) = COPY $x0476 %1(s64) = G_CONSTANT i64 16477 %2(p0) = G_PTR_ADD %0, %1478 %3(s32) = G_LOAD %2 :: (load (s32) from %ir.addr)479 $s0 = COPY %3480...481 482---483name: load_gep_64_s16_fpr484legalized: true485regBankSelected: true486 487registers:488 - { id: 0, class: gpr }489 - { id: 1, class: gpr }490 - { id: 2, class: gpr }491 - { id: 3, class: fpr }492 493body: |494 bb.0:495 liveins: $x0496 497 ; CHECK-LABEL: name: load_gep_64_s16_fpr498 ; CHECK: liveins: $x0499 ; CHECK-NEXT: {{ $}}500 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0501 ; CHECK-NEXT: [[LDRHui:%[0-9]+]]:fpr16 = LDRHui [[COPY]], 32 :: (load (s16) from %ir.addr)502 ; CHECK-NEXT: $h0 = COPY [[LDRHui]]503 %0(p0) = COPY $x0504 %1(s64) = G_CONSTANT i64 64505 %2(p0) = G_PTR_ADD %0, %1506 %3(s16) = G_LOAD %2 :: (load (s16) from %ir.addr)507 $h0 = COPY %3508...509 510---511name: load_gep_32_s8_fpr512legalized: true513regBankSelected: true514 515registers:516 - { id: 0, class: gpr }517 - { id: 1, class: gpr }518 - { id: 2, class: gpr }519 - { id: 3, class: fpr }520 521body: |522 bb.0:523 liveins: $x0524 525 ; CHECK-LABEL: name: load_gep_32_s8_fpr526 ; CHECK: liveins: $x0527 ; CHECK-NEXT: {{ $}}528 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0529 ; CHECK-NEXT: [[LDRBui:%[0-9]+]]:fpr8 = LDRBui [[COPY]], 32 :: (load (s8) from %ir.addr)530 ; CHECK-NEXT: $b0 = COPY [[LDRBui]]531 %0(p0) = COPY $x0532 %1(s64) = G_CONSTANT i64 32533 %2(p0) = G_PTR_ADD %0, %1534 %3(s8) = G_LOAD %2 :: (load (s8) from %ir.addr)535 $b0 = COPY %3536...537---538name: load_v2s32539legalized: true540regBankSelected: true541 542registers:543 - { id: 0, class: gpr }544 - { id: 1, class: fpr }545 546body: |547 bb.0:548 liveins: $x0549 550 ; CHECK-LABEL: name: load_v2s32551 ; CHECK: liveins: $x0552 ; CHECK-NEXT: {{ $}}553 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0554 ; CHECK-NEXT: [[LDRDui:%[0-9]+]]:fpr64 = LDRDui [[COPY]], 0 :: (load (<2 x s32>) from %ir.addr)555 ; CHECK-NEXT: $d0 = COPY [[LDRDui]]556 %0(p0) = COPY $x0557 %1(<2 x s32>) = G_LOAD %0 :: (load (<2 x s32>) from %ir.addr)558 $d0 = COPY %1(<2 x s32>)559...560---561name: load_v2s64562legalized: true563regBankSelected: true564 565registers:566 - { id: 0, class: gpr }567 - { id: 1, class: fpr }568 569body: |570 bb.0:571 liveins: $x0572 573 ; CHECK-LABEL: name: load_v2s64574 ; CHECK: liveins: $x0575 ; CHECK-NEXT: {{ $}}576 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0577 ; CHECK-NEXT: [[LDRQui:%[0-9]+]]:fpr128 = LDRQui [[COPY]], 0 :: (load (<2 x s64>) from %ir.addr)578 ; CHECK-NEXT: $q0 = COPY [[LDRQui]]579 %0(p0) = COPY $x0580 %1(<2 x s64>) = G_LOAD %0 :: (load (<2 x s64>) from %ir.addr)581 $q0 = COPY %1(<2 x s64>)582...583---584name: load_4xi16585alignment: 4586legalized: true587regBankSelected: true588tracksRegLiveness: true589registers:590 - { id: 0, class: gpr }591 - { id: 1, class: fpr }592machineFunctionInfo: {}593body: |594 bb.1 (%ir-block.0):595 liveins: $x0596 597 ; CHECK-LABEL: name: load_4xi16598 ; CHECK: liveins: $x0599 ; CHECK-NEXT: {{ $}}600 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0601 ; CHECK-NEXT: [[LDRDui:%[0-9]+]]:fpr64 = LDRDui [[COPY]], 0 :: (load (<4 x s16>) from %ir.ptr)602 ; CHECK-NEXT: $d0 = COPY [[LDRDui]]603 ; CHECK-NEXT: RET_ReallyLR implicit $d0604 %0:gpr(p0) = COPY $x0605 %1:fpr(<4 x s16>) = G_LOAD %0(p0) :: (load (<4 x s16>) from %ir.ptr)606 $d0 = COPY %1(<4 x s16>)607 RET_ReallyLR implicit $d0608 609...610---611name: load_4xi32612alignment: 4613legalized: true614regBankSelected: true615tracksRegLiveness: true616registers:617 - { id: 0, class: gpr }618 - { id: 1, class: fpr }619machineFunctionInfo: {}620body: |621 bb.1 (%ir-block.0):622 liveins: $x0623 624 ; CHECK-LABEL: name: load_4xi32625 ; CHECK: liveins: $x0626 ; CHECK-NEXT: {{ $}}627 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0628 ; CHECK-NEXT: [[LDRQui:%[0-9]+]]:fpr128 = LDRQui [[COPY]], 0 :: (load (<4 x s32>) from %ir.ptr)629 ; CHECK-NEXT: $q0 = COPY [[LDRQui]]630 ; CHECK-NEXT: RET_ReallyLR implicit $q0631 %0:gpr(p0) = COPY $x0632 %1:fpr(<4 x s32>) = G_LOAD %0(p0) :: (load (<4 x s32>) from %ir.ptr)633 $q0 = COPY %1(<4 x s32>)634 RET_ReallyLR implicit $q0635 636...637---638name: load_8xi16639alignment: 4640legalized: true641regBankSelected: true642tracksRegLiveness: true643registers:644 - { id: 0, class: gpr }645 - { id: 1, class: fpr }646machineFunctionInfo: {}647body: |648 bb.1 (%ir-block.0):649 liveins: $x0650 651 ; CHECK-LABEL: name: load_8xi16652 ; CHECK: liveins: $x0653 ; CHECK-NEXT: {{ $}}654 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0655 ; CHECK-NEXT: [[LDRQui:%[0-9]+]]:fpr128 = LDRQui [[COPY]], 0 :: (load (<8 x s16>) from %ir.ptr)656 ; CHECK-NEXT: $q0 = COPY [[LDRQui]]657 ; CHECK-NEXT: RET_ReallyLR implicit $q0658 %0:gpr(p0) = COPY $x0659 %1:fpr(<8 x s16>) = G_LOAD %0(p0) :: (load (<8 x s16>) from %ir.ptr)660 $q0 = COPY %1(<8 x s16>)661 RET_ReallyLR implicit $q0662 663...664---665name: load_16xi8666alignment: 4667legalized: true668regBankSelected: true669tracksRegLiveness: true670registers:671 - { id: 0, class: gpr }672 - { id: 1, class: fpr }673machineFunctionInfo: {}674body: |675 bb.1 (%ir-block.0):676 liveins: $x0677 678 ; CHECK-LABEL: name: load_16xi8679 ; CHECK: liveins: $x0680 ; CHECK-NEXT: {{ $}}681 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0682 ; CHECK-NEXT: [[LDRQui:%[0-9]+]]:fpr128 = LDRQui [[COPY]], 0 :: (load (<16 x s8>) from %ir.ptr)683 ; CHECK-NEXT: $q0 = COPY [[LDRQui]]684 ; CHECK-NEXT: RET_ReallyLR implicit $q0685 %0:gpr(p0) = COPY $x0686 %1:fpr(<16 x s8>) = G_LOAD %0(p0) :: (load (<16 x s8>) from %ir.ptr)687 $q0 = COPY %1(<16 x s8>)688 RET_ReallyLR implicit $q0689 690...691---692name: anyext_on_fpr693alignment: 4694legalized: true695regBankSelected: true696tracksRegLiveness: true697liveins:698 - { reg: '$x0' }699 - { reg: '$x1' }700 - { reg: '$x2' }701 - { reg: '$w3' }702frameInfo:703 maxAlignment: 1704machineFunctionInfo: {}705body: |706 bb.1:707 liveins: $w3, $x0, $x1, $x2708 709 ; CHECK-LABEL: name: anyext_on_fpr710 ; CHECK: liveins: $w3, $x0, $x1, $x2711 ; CHECK-NEXT: {{ $}}712 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0713 ; CHECK-NEXT: [[LDRHui:%[0-9]+]]:fpr16 = LDRHui [[COPY]], 0 :: (load (s16))714 ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:fpr32 = SUBREG_TO_REG 0, [[LDRHui]], %subreg.hsub715 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32all = COPY [[SUBREG_TO_REG]]716 ; CHECK-NEXT: $w0 = COPY [[COPY1]]717 ; CHECK-NEXT: RET_ReallyLR718 %0:gpr(p0) = COPY $x0719 %16:fpr(s32) = G_LOAD %0(p0) :: (load (s16))720 %24:gpr(s32) = COPY %16(s32)721 $w0 = COPY %24(s32)722 RET_ReallyLR723 724...725---726name: anyext_on_fpr8727alignment: 4728legalized: true729regBankSelected: true730tracksRegLiveness: true731liveins:732 - { reg: '$x0' }733 - { reg: '$x1' }734 - { reg: '$x2' }735 - { reg: '$w3' }736frameInfo:737 maxAlignment: 1738machineFunctionInfo: {}739body: |740 bb.1:741 liveins: $w3, $x0, $x1, $x2742 743 ; CHECK-LABEL: name: anyext_on_fpr8744 ; CHECK: liveins: $w3, $x0, $x1, $x2745 ; CHECK-NEXT: {{ $}}746 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0747 ; CHECK-NEXT: [[LDRBui:%[0-9]+]]:fpr8 = LDRBui [[COPY]], 0 :: (load (s8))748 ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:fpr32 = SUBREG_TO_REG 0, [[LDRBui]], %subreg.bsub749 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32all = COPY [[SUBREG_TO_REG]]750 ; CHECK-NEXT: $w0 = COPY [[COPY1]]751 ; CHECK-NEXT: RET_ReallyLR752 %0:gpr(p0) = COPY $x0753 %16:fpr(s32) = G_LOAD %0(p0) :: (load (s8))754 %24:gpr(s32) = COPY %16(s32)755 $w0 = COPY %24(s32)756 RET_ReallyLR757 758...759---760name: load_s32_gpr_LD1761legalized: true762regBankSelected: true763 764body: |765 bb.0:766 liveins: $q0, $x0767 768 ; CHECK-LABEL: name: load_s32_gpr_LD1769 ; CHECK: liveins: $q0, $x0770 ; CHECK-NEXT: {{ $}}771 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0772 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64sp = COPY $x0773 ; CHECK-NEXT: [[LD1i32_:%[0-9]+]]:fpr128 = LD1i32 [[COPY]], 0, [[COPY1]] :: (load (s32))774 ; CHECK-NEXT: $q0 = COPY [[LD1i32_]]775 ; CHECK-NEXT: RET_ReallyLR implicit $q0776 %0:fpr(<4 x s32>) = COPY $q0777 %1:gpr(p0) = COPY $x0778 %2:fpr(s32) = G_LOAD %1(p0) :: (load (s32))779 %3:gpr(s32) = G_CONSTANT i32 3780 %5:gpr(s64) = G_CONSTANT i64 0781 %4:fpr(<4 x s32>) = G_INSERT_VECTOR_ELT %0, %2(s32), %5(s64)782 $q0 = COPY %4(<4 x s32>)783 RET_ReallyLR implicit $q0784 785...786---787 788name: load_s32_gpr_GIM789legalized: true790regBankSelected: true791 792body: |793 bb.0:794 liveins: $q0, $x0795 ;This test should not select an LD1 instruction as there is a store instruction between G_INSERT_VECTOR_ELT and G_LOAD796 ; CHECK-LABEL: name: load_s32_gpr_GIM797 ; CHECK: liveins: $q0, $x0798 ; CHECK-NEXT: {{ $}}799 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0800 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64sp = COPY $x0801 ; CHECK-NEXT: [[LDRSui:%[0-9]+]]:fpr32 = LDRSui [[COPY1]], 0 :: (load (s32))802 ; CHECK-NEXT: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 3803 ; CHECK-NEXT: STRWui [[MOVi32imm]], [[COPY1]], 0 :: (store (s32))804 ; CHECK-NEXT: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF805 ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[LDRSui]], %subreg.ssub806 ; CHECK-NEXT: [[INSvi32lane:%[0-9]+]]:fpr128 = INSvi32lane [[COPY]], 0, [[INSERT_SUBREG]], 0807 ; CHECK-NEXT: $q0 = COPY [[INSvi32lane]]808 ; CHECK-NEXT: RET_ReallyLR implicit $q0809 %0:fpr(<4 x s32>) = COPY $q0810 %1:gpr(p0) = COPY $x0811 %2:fpr(s32) = G_LOAD %1(p0) :: (load (s32))812 %3:gpr(s32) = G_CONSTANT i32 3813 G_STORE %3(s32), %1(p0) :: (store (s32))814 %5:gpr(s64) = G_CONSTANT i64 0815 %4:fpr(<4 x s32>) = G_INSERT_VECTOR_ELT %0, %2(s32), %5(s64)816 $q0 = COPY %4(<4 x s32>)817 RET_ReallyLR implicit $q0818...819