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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=aarch64-unknown-unknown -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s3 4---5name: logical_imm_64_and6legalized: true7regBankSelected: true8tracksRegLiveness: true9body: |10 bb.0:11 liveins: $x012 ; CHECK-LABEL: name: logical_imm_64_and13 ; CHECK: liveins: $x014 ; CHECK-NEXT: {{ $}}15 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x016 ; CHECK-NEXT: [[ANDXri:%[0-9]+]]:gpr64sp = ANDXri [[COPY]], 409617 ; CHECK-NEXT: $x0 = COPY [[ANDXri]]18 ; CHECK-NEXT: RET_ReallyLR implicit $x019 %0:gpr(s64) = COPY $x020 %1:gpr(s64) = G_CONSTANT i64 121 %2:gpr(s64) = G_AND %0, %1:gpr(s64)22 $x0 = COPY %2:gpr(s64)23 RET_ReallyLR implicit $x024...25---26name: logical_imm_64_or27legalized: true28regBankSelected: true29tracksRegLiveness: true30body: |31 bb.0:32 liveins: $x033 ; CHECK-LABEL: name: logical_imm_64_or34 ; CHECK: liveins: $x035 ; CHECK-NEXT: {{ $}}36 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x037 ; CHECK-NEXT: [[ORRXri:%[0-9]+]]:gpr64sp = ORRXri [[COPY]], 409638 ; CHECK-NEXT: $x0 = COPY [[ORRXri]]39 ; CHECK-NEXT: RET_ReallyLR implicit $x040 %0:gpr(s64) = COPY $x041 %1:gpr(s64) = G_CONSTANT i64 142 %2:gpr(s64) = G_OR %0, %1:gpr(s64)43 $x0 = COPY %2:gpr(s64)44 RET_ReallyLR implicit $x045...46---47name: logical_imm_64_xor48legalized: true49regBankSelected: true50tracksRegLiveness: true51body: |52 bb.0:53 liveins: $x054 ; CHECK-LABEL: name: logical_imm_64_xor55 ; CHECK: liveins: $x056 ; CHECK-NEXT: {{ $}}57 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x058 ; CHECK-NEXT: [[EORXri:%[0-9]+]]:gpr64sp = EORXri [[COPY]], 409659 ; CHECK-NEXT: $x0 = COPY [[EORXri]]60 ; CHECK-NEXT: RET_ReallyLR implicit $x061 %0:gpr(s64) = COPY $x062 %1:gpr(s64) = G_CONSTANT i64 163 %2:gpr(s64) = G_XOR %0, %1:gpr(s64)64 $x0 = COPY %2:gpr(s64)65 RET_ReallyLR implicit $x066...67---68name: logical_imm_32_and69legalized: true70regBankSelected: true71tracksRegLiveness: true72body: |73 bb.0:74 liveins: $w075 ; CHECK-LABEL: name: logical_imm_32_and76 ; CHECK: liveins: $w077 ; CHECK-NEXT: {{ $}}78 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w079 ; CHECK-NEXT: [[ANDWri:%[0-9]+]]:gpr32sp = ANDWri [[COPY]], 080 ; CHECK-NEXT: $w0 = COPY [[ANDWri]]81 ; CHECK-NEXT: RET_ReallyLR implicit $w082 %0:gpr(s32) = COPY $w083 %1:gpr(s32) = G_CONSTANT i32 184 %2:gpr(s32) = G_AND %0, %1:gpr(s32)85 $w0 = COPY %2:gpr(s32)86 RET_ReallyLR implicit $w087...88---89name: logical_imm_32_or90legalized: true91regBankSelected: true92tracksRegLiveness: true93body: |94 bb.0:95 liveins: $w096 ; CHECK-LABEL: name: logical_imm_32_or97 ; CHECK: liveins: $w098 ; CHECK-NEXT: {{ $}}99 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0100 ; CHECK-NEXT: [[ORRWri:%[0-9]+]]:gpr32sp = ORRWri [[COPY]], 0101 ; CHECK-NEXT: $w0 = COPY [[ORRWri]]102 ; CHECK-NEXT: RET_ReallyLR implicit $w0103 %0:gpr(s32) = COPY $w0104 %1:gpr(s32) = G_CONSTANT i32 1105 %2:gpr(s32) = G_OR %0, %1:gpr(s32)106 $w0 = COPY %2:gpr(s32)107 RET_ReallyLR implicit $w0108...109---110name: logical_imm_32_xor111legalized: true112regBankSelected: true113tracksRegLiveness: true114body: |115 bb.0:116 liveins: $w0117 ; CHECK-LABEL: name: logical_imm_32_xor118 ; CHECK: liveins: $w0119 ; CHECK-NEXT: {{ $}}120 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0121 ; CHECK-NEXT: [[EORWri:%[0-9]+]]:gpr32sp = EORWri [[COPY]], 0122 ; CHECK-NEXT: $w0 = COPY [[EORWri]]123 ; CHECK-NEXT: RET_ReallyLR implicit $w0124 %0:gpr(s32) = COPY $w0125 %1:gpr(s32) = G_CONSTANT i32 1126 %2:gpr(s32) = G_XOR %0, %1:gpr(s32)127 $w0 = COPY %2:gpr(s32)128 RET_ReallyLR implicit $w0129...130