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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -O0 -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s3---4name: mul_i64_sext_imm325legalized: true6regBankSelected: true7 8registers:9 - { id: 0, class: gpr }10 - { id: 1, class: gpr }11 - { id: 2, class: gpr }12 - { id: 3, class: gpr }13 14body: |15 bb.0:16 liveins: $w017 18 ; Make sure InstructionSelector is able to match a pattern19 ; with an SDNodeXForm, trunc_imm.20 ; def : Pat<(i64 (mul (sext GPR32:$Rn), (s64imm_32bit:$C))),21 ; (SMADDLrrr GPR32:$Rn, (MOVi32imm (trunc_imm imm:$C)), XZR)>;22 ; CHECK-LABEL: name: mul_i64_sext_imm3223 ; CHECK: liveins: $w024 ; CHECK-NEXT: {{ $}}25 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w026 ; CHECK-NEXT: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 327 ; CHECK-NEXT: [[SMADDLrrr:%[0-9]+]]:gpr64 = SMADDLrrr [[COPY]], [[MOVi32imm]], $xzr28 ; CHECK-NEXT: $x0 = COPY [[SMADDLrrr]]29 %0:gpr(s32) = COPY $w030 %1:gpr(s64) = G_SEXT %0(s32)31 %2:gpr(s64) = G_CONSTANT i64 332 %3:gpr(s64) = G_MUL %1, %233 $x0 = COPY %3(s64)34...35---36name: umulh_v8s1637legalized: true38regBankSelected: true39exposesReturnsTwice: false40tracksRegLiveness: true41liveins:42 - { reg: '$q0', virtual-reg: '' }43body: |44 bb.1:45 liveins: $q0, $q146 47 ; CHECK-LABEL: name: umulh_v8s1648 ; CHECK: liveins: $q0, $q149 ; CHECK-NEXT: {{ $}}50 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q051 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q152 ; CHECK-NEXT: [[UMULLv8i16_v4i32_:%[0-9]+]]:fpr128 = UMULLv8i16_v4i32 [[COPY]], [[COPY1]]53 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr64 = COPY [[COPY1]].dsub54 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:fpr64 = COPY [[COPY]].dsub55 ; CHECK-NEXT: [[UMULLv4i16_v4i32_:%[0-9]+]]:fpr128 = UMULLv4i16_v4i32 [[COPY3]], [[COPY2]]56 ; CHECK-NEXT: %mul:fpr128 = UZP2v8i16 [[UMULLv4i16_v4i32_]], [[UMULLv8i16_v4i32_]]57 ; CHECK-NEXT: $q0 = COPY %mul58 ; CHECK-NEXT: RET_ReallyLR implicit $q059 %0:fpr(<8 x s16>) = COPY $q060 %1:fpr(<8 x s16>) = COPY $q161 %mul:fpr(<8 x s16>) = G_UMULH %0, %162 $q0 = COPY %mul(<8 x s16>)63 RET_ReallyLR implicit $q064 65...66---67name: umulh_v16s868legalized: true69regBankSelected: true70exposesReturnsTwice: false71tracksRegLiveness: true72liveins:73 - { reg: '$q0', virtual-reg: '' }74body: |75 bb.1:76 liveins: $q0, $q177 78 ; CHECK-LABEL: name: umulh_v16s879 ; CHECK: liveins: $q0, $q180 ; CHECK-NEXT: {{ $}}81 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q082 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q183 ; CHECK-NEXT: [[UMULLv16i8_v8i16_:%[0-9]+]]:fpr128 = UMULLv16i8_v8i16 [[COPY]], [[COPY1]]84 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr64 = COPY [[COPY1]].dsub85 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:fpr64 = COPY [[COPY]].dsub86 ; CHECK-NEXT: [[UMULLv8i8_v8i16_:%[0-9]+]]:fpr128 = UMULLv8i8_v8i16 [[COPY3]], [[COPY2]]87 ; CHECK-NEXT: %mul:fpr128 = UZP2v16i8 [[UMULLv8i8_v8i16_]], [[UMULLv16i8_v8i16_]]88 ; CHECK-NEXT: $q0 = COPY %mul89 ; CHECK-NEXT: RET_ReallyLR implicit $q090 %0:fpr(<16 x s8>) = COPY $q091 %1:fpr(<16 x s8>) = COPY $q192 %mul:fpr(<16 x s8>) = G_UMULH %0, %193 $q0 = COPY %mul(<16 x s8>)94 RET_ReallyLR implicit $q095 96...97---98name: umulh_v4s3299legalized: true100regBankSelected: true101exposesReturnsTwice: false102tracksRegLiveness: true103liveins:104 - { reg: '$q0', virtual-reg: '' }105body: |106 bb.1:107 liveins: $q0, $q1108 109 ; CHECK-LABEL: name: umulh_v4s32110 ; CHECK: liveins: $q0, $q1111 ; CHECK-NEXT: {{ $}}112 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0113 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1114 ; CHECK-NEXT: [[UMULLv4i32_v2i64_:%[0-9]+]]:fpr128 = UMULLv4i32_v2i64 [[COPY]], [[COPY1]]115 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr64 = COPY [[COPY1]].dsub116 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:fpr64 = COPY [[COPY]].dsub117 ; CHECK-NEXT: [[UMULLv2i32_v2i64_:%[0-9]+]]:fpr128 = UMULLv2i32_v2i64 [[COPY3]], [[COPY2]]118 ; CHECK-NEXT: %mul:fpr128 = UZP2v4i32 [[UMULLv2i32_v2i64_]], [[UMULLv4i32_v2i64_]]119 ; CHECK-NEXT: $q0 = COPY %mul120 ; CHECK-NEXT: RET_ReallyLR implicit $q0121 %0:fpr(<4 x s32>) = COPY $q0122 %1:fpr(<4 x s32>) = COPY $q1123 %mul:fpr(<4 x s32>) = G_UMULH %0, %1124 $q0 = COPY %mul(<4 x s32>)125 RET_ReallyLR implicit $q0126 127...128---129name: smulh_v8s16130legalized: true131regBankSelected: true132exposesReturnsTwice: false133tracksRegLiveness: true134liveins:135 - { reg: '$q0', virtual-reg: '' }136body: |137 bb.1:138 liveins: $q0, $q1139 140 ; CHECK-LABEL: name: smulh_v8s16141 ; CHECK: liveins: $q0, $q1142 ; CHECK-NEXT: {{ $}}143 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0144 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1145 ; CHECK-NEXT: [[SMULLv8i16_v4i32_:%[0-9]+]]:fpr128 = SMULLv8i16_v4i32 [[COPY]], [[COPY1]]146 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr64 = COPY [[COPY1]].dsub147 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:fpr64 = COPY [[COPY]].dsub148 ; CHECK-NEXT: [[SMULLv4i16_v4i32_:%[0-9]+]]:fpr128 = SMULLv4i16_v4i32 [[COPY3]], [[COPY2]]149 ; CHECK-NEXT: %mul:fpr128 = UZP2v8i16 [[SMULLv4i16_v4i32_]], [[SMULLv8i16_v4i32_]]150 ; CHECK-NEXT: $q0 = COPY %mul151 ; CHECK-NEXT: RET_ReallyLR implicit $q0152 %0:fpr(<8 x s16>) = COPY $q0153 %1:fpr(<8 x s16>) = COPY $q1154 %mul:fpr(<8 x s16>) = G_SMULH %0, %1155 $q0 = COPY %mul(<8 x s16>)156 RET_ReallyLR implicit $q0157 158...159---160name: smulh_v16s8161legalized: true162regBankSelected: true163exposesReturnsTwice: false164tracksRegLiveness: true165liveins:166 - { reg: '$q0', virtual-reg: '' }167body: |168 bb.1:169 liveins: $q0, $q1170 171 ; CHECK-LABEL: name: smulh_v16s8172 ; CHECK: liveins: $q0, $q1173 ; CHECK-NEXT: {{ $}}174 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0175 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1176 ; CHECK-NEXT: [[SMULLv16i8_v8i16_:%[0-9]+]]:fpr128 = SMULLv16i8_v8i16 [[COPY]], [[COPY1]]177 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr64 = COPY [[COPY1]].dsub178 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:fpr64 = COPY [[COPY]].dsub179 ; CHECK-NEXT: [[SMULLv8i8_v8i16_:%[0-9]+]]:fpr128 = SMULLv8i8_v8i16 [[COPY3]], [[COPY2]]180 ; CHECK-NEXT: %mul:fpr128 = UZP2v16i8 [[SMULLv8i8_v8i16_]], [[SMULLv16i8_v8i16_]]181 ; CHECK-NEXT: $q0 = COPY %mul182 ; CHECK-NEXT: RET_ReallyLR implicit $q0183 %0:fpr(<16 x s8>) = COPY $q0184 %1:fpr(<16 x s8>) = COPY $q1185 %mul:fpr(<16 x s8>) = G_SMULH %0, %1186 $q0 = COPY %mul(<16 x s8>)187 RET_ReallyLR implicit $q0188 189...190---191name: smulh_v4s32192legalized: true193regBankSelected: true194exposesReturnsTwice: false195tracksRegLiveness: true196liveins:197 - { reg: '$q0', virtual-reg: '' }198body: |199 bb.1:200 liveins: $q0, $q1201 202 ; CHECK-LABEL: name: smulh_v4s32203 ; CHECK: liveins: $q0, $q1204 ; CHECK-NEXT: {{ $}}205 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0206 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1207 ; CHECK-NEXT: [[SMULLv4i32_v2i64_:%[0-9]+]]:fpr128 = SMULLv4i32_v2i64 [[COPY]], [[COPY1]]208 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr64 = COPY [[COPY1]].dsub209 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:fpr64 = COPY [[COPY]].dsub210 ; CHECK-NEXT: [[SMULLv2i32_v2i64_:%[0-9]+]]:fpr128 = SMULLv2i32_v2i64 [[COPY3]], [[COPY2]]211 ; CHECK-NEXT: %mul:fpr128 = UZP2v4i32 [[SMULLv2i32_v2i64_]], [[SMULLv4i32_v2i64_]]212 ; CHECK-NEXT: $q0 = COPY %mul213 ; CHECK-NEXT: RET_ReallyLR implicit $q0214 %0:fpr(<4 x s32>) = COPY $q0215 %1:fpr(<4 x s32>) = COPY $q1216 %mul:fpr(<4 x s32>) = G_SMULH %0, %1217 $q0 = COPY %mul(<4 x s32>)218 RET_ReallyLR implicit $q0219 220...221