35 lines · plain
1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=aarch64-- -mattr=+neon,+fullfp16 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s3 4--- |5 target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"6 7 define void @vcvtfxu2fp_s64_fpr() { ret void }8...9 10---11# Check that we select a 64-bit FPR vcvtfxu2fp intrinsic into UCVTFd for FPR64.12name: vcvtfxu2fp_s64_fpr13legalized: true14regBankSelected: true15 16registers:17 - { id: 0, class: fpr }18 - { id: 1, class: gpr }19 - { id: 2, class: fpr }20 21body: |22 bb.0:23 liveins: $d024 25 ; CHECK-LABEL: name: vcvtfxu2fp_s64_fpr26 ; CHECK: liveins: $d027 ; CHECK-NEXT: {{ $}}28 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d029 ; CHECK-NEXT: [[UCVTFd:%[0-9]+]]:fpr64 = UCVTFd [[COPY]], 1230 ; CHECK-NEXT: $d1 = COPY [[UCVTFd]]31 %0(s64) = COPY $d032 %2(s64) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.vcvtfxu2fp.f64), %0, 1233 $d1 = COPY %2(s64)34...35