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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=aarch64 -run-pass=instruction-select -verify-machineinstrs -global-isel-abort=1 %s -o - | FileCheck %s3---4name: add_B5alignment: 46legalized: true7regBankSelected: true8tracksRegLiveness: true9liveins:10 - { reg: '$x0' }11body: |12 bb.1:13 liveins: $x014 15 ; CHECK-LABEL: name: add_B16 ; CHECK: liveins: $x017 ; CHECK-NEXT: {{ $}}18 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x019 ; CHECK-NEXT: [[LDRQui:%[0-9]+]]:fpr128 = LDRQui [[COPY]], 0 :: (load (<16 x s8>))20 ; CHECK-NEXT: [[ADDVv16i8v:%[0-9]+]]:fpr8 = ADDVv16i8v [[LDRQui]]21 ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:fpr32 = SUBREG_TO_REG 0, [[ADDVv16i8v]], %subreg.bsub22 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32all = COPY [[SUBREG_TO_REG]]23 ; CHECK-NEXT: $w0 = COPY [[COPY1]]24 ; CHECK-NEXT: RET_ReallyLR implicit $w025 %0:gpr(p0) = COPY $x026 %1:fpr(<16 x s8>) = G_LOAD %0(p0) :: (load (<16 x s8>))27 %2:fpr(s8) = G_VECREDUCE_ADD %1(<16 x s8>)28 %4:gpr(s8) = COPY %2(s8)29 %3:gpr(s32) = G_ANYEXT %4(s8)30 $w0 = COPY %3(s32)31 RET_ReallyLR implicit $w032 33...34---35name: add_H36alignment: 437legalized: true38regBankSelected: true39tracksRegLiveness: true40liveins:41 - { reg: '$x0' }42body: |43 bb.1:44 liveins: $x045 46 ; CHECK-LABEL: name: add_H47 ; CHECK: liveins: $x048 ; CHECK-NEXT: {{ $}}49 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x050 ; CHECK-NEXT: [[LDRQui:%[0-9]+]]:fpr128 = LDRQui [[COPY]], 0 :: (load (<8 x s16>))51 ; CHECK-NEXT: [[ADDVv8i16v:%[0-9]+]]:fpr16 = ADDVv8i16v [[LDRQui]]52 ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:fpr32 = SUBREG_TO_REG 0, [[ADDVv8i16v]], %subreg.hsub53 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32all = COPY [[SUBREG_TO_REG]]54 ; CHECK-NEXT: $w0 = COPY [[COPY1]]55 ; CHECK-NEXT: RET_ReallyLR implicit $w056 %0:gpr(p0) = COPY $x057 %1:fpr(<8 x s16>) = G_LOAD %0(p0) :: (load (<8 x s16>))58 %2:fpr(s16) = G_VECREDUCE_ADD %1(<8 x s16>)59 %4:gpr(s16) = COPY %2(s16)60 %3:gpr(s32) = G_ANYEXT %4(s16)61 $w0 = COPY %3(s32)62 RET_ReallyLR implicit $w063 64...65---66name: add_S67alignment: 468legalized: true69regBankSelected: true70tracksRegLiveness: true71liveins:72 - { reg: '$x0' }73body: |74 bb.1:75 liveins: $x076 77 ; CHECK-LABEL: name: add_S78 ; CHECK: liveins: $x079 ; CHECK-NEXT: {{ $}}80 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x081 ; CHECK-NEXT: [[LDRQui:%[0-9]+]]:fpr128 = LDRQui [[COPY]], 0 :: (load (<4 x s32>))82 ; CHECK-NEXT: [[ADDVv4i32v:%[0-9]+]]:fpr32 = ADDVv4i32v [[LDRQui]]83 ; CHECK-NEXT: $w0 = COPY [[ADDVv4i32v]]84 ; CHECK-NEXT: RET_ReallyLR implicit $w085 %0:gpr(p0) = COPY $x086 %1:fpr(<4 x s32>) = G_LOAD %0(p0) :: (load (<4 x s32>))87 %2:fpr(s32) = G_VECREDUCE_ADD %1(<4 x s32>)88 $w0 = COPY %2(s32)89 RET_ReallyLR implicit $w090 91...92---93name: add_S_v2i3294alignment: 495legalized: true96regBankSelected: true97tracksRegLiveness: true98liveins:99 - { reg: '$x0' }100body: |101 bb.1:102 liveins: $x0103 104 ; CHECK-LABEL: name: add_S_v2i32105 ; CHECK: liveins: $x0106 ; CHECK-NEXT: {{ $}}107 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0108 ; CHECK-NEXT: [[LDRDui:%[0-9]+]]:fpr64 = LDRDui [[COPY]], 0 :: (load (<2 x s32>))109 ; CHECK-NEXT: [[ADDPv2i32_:%[0-9]+]]:fpr64 = ADDPv2i32 [[LDRDui]], [[LDRDui]]110 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr32 = COPY [[ADDPv2i32_]].ssub111 ; CHECK-NEXT: $w0 = COPY [[COPY1]]112 ; CHECK-NEXT: RET_ReallyLR implicit $w0113 %0:gpr(p0) = COPY $x0114 %1:fpr(<2 x s32>) = G_LOAD %0(p0) :: (load (<2 x s32>))115 %2:fpr(s32) = G_VECREDUCE_ADD %1(<2 x s32>)116 $w0 = COPY %2(s32)117 RET_ReallyLR implicit $w0118 119...120---121name: add_D122alignment: 4123legalized: true124regBankSelected: true125tracksRegLiveness: true126liveins:127 - { reg: '$x0' }128body: |129 bb.1:130 liveins: $x0131 132 ; CHECK-LABEL: name: add_D133 ; CHECK: liveins: $x0134 ; CHECK-NEXT: {{ $}}135 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0136 ; CHECK-NEXT: [[LDRQui:%[0-9]+]]:fpr128 = LDRQui [[COPY]], 0 :: (load (<2 x s64>))137 ; CHECK-NEXT: [[ADDPv2i64p:%[0-9]+]]:fpr64 = ADDPv2i64p [[LDRQui]]138 ; CHECK-NEXT: $x0 = COPY [[ADDPv2i64p]]139 ; CHECK-NEXT: RET_ReallyLR implicit $x0140 %0:gpr(p0) = COPY $x0141 %1:fpr(<2 x s64>) = G_LOAD %0(p0) :: (load (<2 x s64>))142 %2:fpr(s64) = G_VECREDUCE_ADD %1(<2 x s64>)143 $x0 = COPY %2(s64)144 RET_ReallyLR implicit $x0145 146...147