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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=aarch64 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s3 4...5---6name: fold7legalized: true8regBankSelected: true9tracksRegLiveness: true10body: |11 bb.0:12 liveins: $w0, $w113 14 ; This should not have an UBFMXri, since ADDWrr implicitly gives us the15 ; zext.16 17 ; CHECK-LABEL: name: fold18 ; CHECK: liveins: $w0, $w119 ; CHECK-NEXT: {{ $}}20 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w021 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w122 ; CHECK-NEXT: [[ADDWrr:%[0-9]+]]:gpr32 = ADDWrr [[COPY1]], [[COPY]]23 ; CHECK-NEXT: [[ORRWrs:%[0-9]+]]:gpr32 = ORRWrs $wzr, [[ADDWrr]], 024 ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[ORRWrs]], %subreg.sub_3225 ; CHECK-NEXT: $x0 = COPY [[SUBREG_TO_REG]]26 ; CHECK-NEXT: RET_ReallyLR implicit $x027 %0:gpr(s32) = COPY $w028 %1:gpr(s32) = COPY $w129 %2:gpr(s32) = G_ADD %1, %030 %3:gpr(s64) = G_ZEXT %2(s32)31 $x0 = COPY %3(s64)32 RET_ReallyLR implicit $x033 34...35---36name: dont_fold_s1637legalized: true38regBankSelected: true39tracksRegLiveness: true40body: |41 bb.0:42 liveins: $w0, $w143 44 ; We should have a UBFMXri here, because we only do this for zero extends45 ; from 32 bits to 64 bits.46 47 ; CHECK-LABEL: name: dont_fold_s1648 ; CHECK: liveins: $w0, $w149 ; CHECK-NEXT: {{ $}}50 ; CHECK-NEXT: [[DEF:%[0-9]+]]:gpr32 = IMPLICIT_DEF51 ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[DEF]], %subreg.sub_3252 ; CHECK-NEXT: [[UBFMXri:%[0-9]+]]:gpr64 = UBFMXri [[SUBREG_TO_REG]], 0, 1553 ; CHECK-NEXT: $x0 = COPY [[UBFMXri]]54 ; CHECK-NEXT: RET_ReallyLR implicit $x055 %0:gpr(s16) = G_IMPLICIT_DEF56 %3:gpr(s64) = G_ZEXT %0(s16)57 $x0 = COPY %3(s64)58 RET_ReallyLR implicit $x059 60...61---62name: dont_fold_copy63legalized: true64regBankSelected: true65tracksRegLiveness: true66body: |67 bb.0:68 liveins: $w069 70 ; We should have a ORRWrs here, because isDef32 disallows copies.71 72 ; CHECK-LABEL: name: dont_fold_copy73 ; CHECK: liveins: $w074 ; CHECK-NEXT: {{ $}}75 ; CHECK-NEXT: %copy:gpr32 = COPY $w076 ; CHECK-NEXT: [[ORRWrs:%[0-9]+]]:gpr32 = ORRWrs $wzr, %copy, 077 ; CHECK-NEXT: %zext:gpr64 = SUBREG_TO_REG 0, [[ORRWrs]], %subreg.sub_3278 ; CHECK-NEXT: $x0 = COPY %zext79 ; CHECK-NEXT: RET_ReallyLR implicit $x080 %copy:gpr(s32) = COPY $w081 %zext:gpr(s64) = G_ZEXT %copy(s32)82 $x0 = COPY %zext(s64)83 RET_ReallyLR implicit $x084 85...86---87name: dont_fold_bitcast88legalized: true89regBankSelected: true90tracksRegLiveness: true91body: |92 bb.0:93 liveins: $w094 95 ; We should have a ORRWrs here, because isDef32 disallows bitcasts.96 97 ; CHECK-LABEL: name: dont_fold_bitcast98 ; CHECK: liveins: $w099 ; CHECK-NEXT: {{ $}}100 ; CHECK-NEXT: %copy:gpr32all = COPY $w0101 ; CHECK-NEXT: %bitcast1:gpr32 = COPY %copy102 ; CHECK-NEXT: [[ORRWrs:%[0-9]+]]:gpr32 = ORRWrs $wzr, %bitcast1, 0103 ; CHECK-NEXT: %zext:gpr64 = SUBREG_TO_REG 0, [[ORRWrs]], %subreg.sub_32104 ; CHECK-NEXT: $x0 = COPY %zext105 ; CHECK-NEXT: RET_ReallyLR implicit $x0106 %copy:gpr(s32) = COPY $w0107 %bitcast0:gpr(<4 x s8>) = G_BITCAST %copy(s32)108 %bitcast1:gpr(s32) = G_BITCAST %bitcast0109 %zext:gpr(s64) = G_ZEXT %bitcast1(s32)110 $x0 = COPY %zext(s64)111 RET_ReallyLR implicit $x0112 113...114---115name: dont_fold_trunc116legalized: true117regBankSelected: true118tracksRegLiveness: true119body: |120 bb.0:121 liveins: $x0122 123 ; We should have a ORRWrs here, because isDef32 disallows truncs.124 125 ; CHECK-LABEL: name: dont_fold_trunc126 ; CHECK: liveins: $x0127 ; CHECK-NEXT: {{ $}}128 ; CHECK-NEXT: %copy:gpr64sp = COPY $x0129 ; CHECK-NEXT: %trunc:gpr32common = COPY %copy.sub_32130 ; CHECK-NEXT: [[ORRWrs:%[0-9]+]]:gpr32 = ORRWrs $wzr, %trunc, 0131 ; CHECK-NEXT: %zext:gpr64 = SUBREG_TO_REG 0, [[ORRWrs]], %subreg.sub_32132 ; CHECK-NEXT: $x0 = COPY %zext133 ; CHECK-NEXT: RET_ReallyLR implicit $x0134 %copy:gpr(s64) = COPY $x0135 %trunc:gpr(s32) = G_TRUNC %copy(s64)136 %zext:gpr(s64) = G_ZEXT %trunc(s32)137 $x0 = COPY %zext(s64)138 RET_ReallyLR implicit $x0139 140...141---142name: dont_fold_phi143legalized: true144regBankSelected: true145tracksRegLiveness: true146body: |147 ; CHECK-LABEL: name: dont_fold_phi148 ; CHECK: bb.0:149 ; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)150 ; CHECK-NEXT: liveins: $w0, $w1, $w2151 ; CHECK-NEXT: {{ $}}152 ; CHECK-NEXT: %copy1:gpr32all = COPY $w0153 ; CHECK-NEXT: %copy2:gpr32all = COPY $w1154 ; CHECK-NEXT: %cond_wide:gpr32 = COPY $w2155 ; CHECK-NEXT: TBNZW %cond_wide, 0, %bb.1156 ; CHECK-NEXT: B %bb.2157 ; CHECK-NEXT: {{ $}}158 ; CHECK-NEXT: bb.1:159 ; CHECK-NEXT: successors: %bb.2(0x80000000)160 ; CHECK-NEXT: {{ $}}161 ; CHECK-NEXT: bb.2:162 ; CHECK-NEXT: %phi:gpr32 = PHI %copy1, %bb.0, %copy2, %bb.1163 ; CHECK-NEXT: [[ORRWrs:%[0-9]+]]:gpr32 = ORRWrs $wzr, %phi, 0164 ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[ORRWrs]], %subreg.sub_32165 ; CHECK-NEXT: $x0 = COPY [[SUBREG_TO_REG]]166 ; CHECK-NEXT: RET_ReallyLR implicit $x0167 ; We should have a ORRWrs here, because isDef32 disallows phis.168 169 bb.0:170 liveins: $w0, $w1, $w2171 172 %copy1:gpr(s32) = COPY $w0173 %copy2:gpr(s32) = COPY $w1174 %cond_wide:gpr(s32) = COPY $w2175 G_BRCOND %cond_wide, %bb.1176 G_BR %bb.2177 178 bb.1:179 180 bb.2:181 %phi:gpr(s32) = G_PHI %copy1(s32), %bb.0, %copy2(s32), %bb.1182 %5:gpr(s64) = G_ZEXT %phi(s32)183 $x0 = COPY %5(s64)184 RET_ReallyLR implicit $x0185 186...187---188name: dont_look_through_copy189legalized: true190regBankSelected: true191tracksRegLiveness: true192body: |193 bb.0:194 liveins: $w0, $w1195 196 ; Make sure we don't walk past the copy.197 198 ; CHECK-LABEL: name: dont_look_through_copy199 ; CHECK: liveins: $w0, $w1200 ; CHECK-NEXT: {{ $}}201 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0202 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1203 ; CHECK-NEXT: [[ADDWrr:%[0-9]+]]:gpr32 = ADDWrr [[COPY1]], [[COPY]]204 ; CHECK-NEXT: [[ORRWrs:%[0-9]+]]:gpr32 = ORRWrs $wzr, [[ADDWrr]], 0205 ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[ORRWrs]], %subreg.sub_32206 ; CHECK-NEXT: $x0 = COPY [[SUBREG_TO_REG]]207 ; CHECK-NEXT: RET_ReallyLR implicit $x0208 %0:gpr(s32) = COPY $w0209 %1:gpr(s32) = COPY $w1210 %2:gpr(s32) = G_ADD %1, %0211 %3:gpr(s32) = COPY %2(s32)212 %4:gpr(s64) = G_ZEXT %3(s32)213 $x0 = COPY %4(s64)214 RET_ReallyLR implicit $x0215