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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple aarch64 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s3#4# Test selecting G_REV instructions.5#6# Each test is named like:7#8# (G_REV_VERSION)_(INSTRUCTION_PRODUCED)9#10# Each of these patterns come from AArch64GenGlobalISel.inc.11#12 13...14---15name: rev64_REV64v2i3216alignment: 417legalized: true18regBankSelected: true19tracksRegLiveness: true20body: |21 bb.0.entry:22 liveins: $d023 ; CHECK-LABEL: name: rev64_REV64v2i3224 ; CHECK: liveins: $d025 ; CHECK-NEXT: {{ $}}26 ; CHECK-NEXT: %copy:fpr64 = COPY $d027 ; CHECK-NEXT: %rev:fpr64 = REV64v2i32 %copy28 ; CHECK-NEXT: $d0 = COPY %rev29 ; CHECK-NEXT: RET_ReallyLR implicit $d030 %copy:fpr(<2 x s32>) = COPY $d031 %rev:fpr(<2 x s32>) = G_REV64 %copy32 $d0 = COPY %rev(<2 x s32>)33 RET_ReallyLR implicit $d034 35...36---37name: rev64_REV64v4i1638alignment: 439legalized: true40regBankSelected: true41tracksRegLiveness: true42body: |43 bb.0.entry:44 liveins: $d045 ; CHECK-LABEL: name: rev64_REV64v4i1646 ; CHECK: liveins: $d047 ; CHECK-NEXT: {{ $}}48 ; CHECK-NEXT: %copy:fpr64 = COPY $d049 ; CHECK-NEXT: %rev:fpr64 = REV64v4i16 %copy50 ; CHECK-NEXT: $d0 = COPY %rev51 ; CHECK-NEXT: RET_ReallyLR implicit $d052 %copy:fpr(<4 x s16>) = COPY $d053 %rev:fpr(<4 x s16>) = G_REV64 %copy54 $d0 = COPY %rev(<4 x s16>)55 RET_ReallyLR implicit $d056 57...58---59name: rev64_REV64v4i3260alignment: 461legalized: true62regBankSelected: true63tracksRegLiveness: true64body: |65 bb.0.entry:66 liveins: $q067 ; CHECK-LABEL: name: rev64_REV64v4i3268 ; CHECK: liveins: $q069 ; CHECK-NEXT: {{ $}}70 ; CHECK-NEXT: %copy:fpr128 = COPY $q071 ; CHECK-NEXT: %rev:fpr128 = REV64v4i32 %copy72 ; CHECK-NEXT: $q0 = COPY %rev73 ; CHECK-NEXT: RET_ReallyLR implicit $q074 %copy:fpr(<4 x s32>) = COPY $q075 %rev:fpr(<4 x s32>) = G_REV64 %copy76 $q0 = COPY %rev(<4 x s32>)77 RET_ReallyLR implicit $q078 79...80---81name: rev64_REV64v8i882alignment: 483legalized: true84regBankSelected: true85tracksRegLiveness: true86body: |87 bb.0.entry:88 liveins: $q089 ; CHECK-LABEL: name: rev64_REV64v8i890 ; CHECK: liveins: $q091 ; CHECK-NEXT: {{ $}}92 ; CHECK-NEXT: %copy:fpr64 = COPY $d093 ; CHECK-NEXT: %rev:fpr64 = REV64v8i8 %copy94 ; CHECK-NEXT: $d0 = COPY %rev95 ; CHECK-NEXT: RET_ReallyLR implicit $d096 %copy:fpr(<8 x s8>) = COPY $d097 %rev:fpr(<8 x s8>) = G_REV64 %copy98 $d0 = COPY %rev(<8 x s8>)99 RET_ReallyLR implicit $d0100 101...102---103name: rev64_REV64v8i16104alignment: 4105legalized: true106regBankSelected: true107tracksRegLiveness: true108body: |109 bb.0.entry:110 liveins: $q0111 ; CHECK-LABEL: name: rev64_REV64v8i16112 ; CHECK: liveins: $q0113 ; CHECK-NEXT: {{ $}}114 ; CHECK-NEXT: %copy:fpr128 = COPY $q0115 ; CHECK-NEXT: %rev:fpr128 = REV64v8i16 %copy116 ; CHECK-NEXT: $q0 = COPY %rev117 ; CHECK-NEXT: RET_ReallyLR implicit $q0118 %copy:fpr(<8 x s16>) = COPY $q0119 %rev:fpr(<8 x s16>) = G_REV64 %copy120 $q0 = COPY %rev(<8 x s16>)121 RET_ReallyLR implicit $q0122 123...124---125name: rev64_REV64v16i8126alignment: 4127legalized: true128regBankSelected: true129tracksRegLiveness: true130body: |131 bb.0.entry:132 liveins: $q0133 ; CHECK-LABEL: name: rev64_REV64v16i8134 ; CHECK: liveins: $q0135 ; CHECK-NEXT: {{ $}}136 ; CHECK-NEXT: %copy:fpr128 = COPY $q0137 ; CHECK-NEXT: %rev:fpr128 = REV64v16i8 %copy138 ; CHECK-NEXT: $q0 = COPY %rev139 ; CHECK-NEXT: RET_ReallyLR implicit $q0140 %copy:fpr(<16 x s8>) = COPY $q0141 %rev:fpr(<16 x s8>) = G_REV64 %copy142 $q0 = COPY %rev(<16 x s8>)143 RET_ReallyLR implicit $q0144 145...146---147name: rev32_REV32v4i16148alignment: 4149legalized: true150regBankSelected: true151tracksRegLiveness: true152body: |153 bb.0.entry:154 liveins: $d0155 ; CHECK-LABEL: name: rev32_REV32v4i16156 ; CHECK: liveins: $d0157 ; CHECK-NEXT: {{ $}}158 ; CHECK-NEXT: %copy:fpr64 = COPY $d0159 ; CHECK-NEXT: %rev:fpr64 = REV32v4i16 %copy160 ; CHECK-NEXT: $d0 = COPY %rev161 ; CHECK-NEXT: RET_ReallyLR implicit $d0162 %copy:fpr(<4 x s16>) = COPY $d0163 %rev:fpr(<4 x s16>) = G_REV32 %copy164 $d0 = COPY %rev(<4 x s16>)165 RET_ReallyLR implicit $d0166 167...168---169name: rev32_REV32v8i8170alignment: 4171legalized: true172regBankSelected: true173tracksRegLiveness: true174body: |175 bb.0.entry:176 liveins: $d0177 ; CHECK-LABEL: name: rev32_REV32v8i8178 ; CHECK: liveins: $d0179 ; CHECK-NEXT: {{ $}}180 ; CHECK-NEXT: %copy:fpr64 = COPY $d0181 ; CHECK-NEXT: %rev:fpr64 = REV32v8i8 %copy182 ; CHECK-NEXT: $d0 = COPY %rev183 ; CHECK-NEXT: RET_ReallyLR implicit $d0184 %copy:fpr(<8 x s8>) = COPY $d0185 %rev:fpr(<8 x s8>) = G_REV32 %copy186 $d0 = COPY %rev(<8 x s8>)187 RET_ReallyLR implicit $d0188 189...190---191name: rev32_REV32v8i16192alignment: 4193legalized: true194regBankSelected: true195tracksRegLiveness: true196body: |197 bb.0.entry:198 liveins: $q0199 ; CHECK-LABEL: name: rev32_REV32v8i16200 ; CHECK: liveins: $q0201 ; CHECK-NEXT: {{ $}}202 ; CHECK-NEXT: %copy:fpr128 = COPY $q0203 ; CHECK-NEXT: %rev:fpr128 = REV32v8i16 %copy204 ; CHECK-NEXT: $q0 = COPY %rev205 ; CHECK-NEXT: RET_ReallyLR implicit $q0206 %copy:fpr(<8 x s16>) = COPY $q0207 %rev:fpr(<8 x s16>) = G_REV32 %copy208 $q0 = COPY %rev(<8 x s16>)209 RET_ReallyLR implicit $q0210 211...212---213name: rev32_REV32v16i8214alignment: 4215legalized: true216regBankSelected: true217tracksRegLiveness: true218body: |219 bb.0.entry:220 liveins: $q0221 ; CHECK-LABEL: name: rev32_REV32v16i8222 ; CHECK: liveins: $q0223 ; CHECK-NEXT: {{ $}}224 ; CHECK-NEXT: %copy:fpr128 = COPY $q0225 ; CHECK-NEXT: %rev:fpr128 = REV32v16i8 %copy226 ; CHECK-NEXT: $q0 = COPY %rev227 ; CHECK-NEXT: RET_ReallyLR implicit $q0228 %copy:fpr(<16 x s8>) = COPY $q0229 %rev:fpr(<16 x s8>) = G_REV32 %copy230 $q0 = COPY %rev(<16 x s8>)231 RET_ReallyLR implicit $q0232 233...234---235name: rev16_REV16v8i8236alignment: 4237legalized: true238regBankSelected: true239tracksRegLiveness: true240body: |241 bb.0.entry:242 liveins: $q0243 ; CHECK-LABEL: name: rev16_REV16v8i8244 ; CHECK: liveins: $q0245 ; CHECK-NEXT: {{ $}}246 ; CHECK-NEXT: %copy:fpr64 = COPY $d0247 ; CHECK-NEXT: %rev:fpr64 = REV16v8i8 %copy248 ; CHECK-NEXT: $d0 = COPY %rev249 ; CHECK-NEXT: RET_ReallyLR implicit $d0250 %copy:fpr(<8 x s8>) = COPY $d0251 %rev:fpr(<8 x s8>) = G_REV16 %copy252 $d0 = COPY %rev(<8 x s8>)253 RET_ReallyLR implicit $d0254 255...256---257name: rev16_REV16v16i8258alignment: 4259legalized: true260regBankSelected: true261tracksRegLiveness: true262body: |263 bb.0.entry:264 liveins: $q0265 ; CHECK-LABEL: name: rev16_REV16v16i8266 ; CHECK: liveins: $q0267 ; CHECK-NEXT: {{ $}}268 ; CHECK-NEXT: %copy:fpr128 = COPY $q0269 ; CHECK-NEXT: %rev:fpr128 = REV16v16i8 %copy270 ; CHECK-NEXT: $q0 = COPY %rev271 ; CHECK-NEXT: RET_ReallyLR implicit $q0272 %copy:fpr(<16 x s8>) = COPY $q0273 %rev:fpr(<16 x s8>) = G_REV16 %copy274 $q0 = COPY %rev(<16 x s8>)275 RET_ReallyLR implicit $q0276