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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=aarch64-- -O0 -run-pass=instruction-select -verify-machineinstrs %s -global-isel-abort=1 -o - | FileCheck %s3---4name: shl_cimm_325legalized: true6regBankSelected: true7body: |8 bb.1:9 liveins: $w010 11 ; CHECK-LABEL: name: shl_cimm_3212 ; CHECK: liveins: $w013 ; CHECK-NEXT: {{ $}}14 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w015 ; CHECK-NEXT: [[UBFMWri:%[0-9]+]]:gpr32 = UBFMWri [[COPY]], 24, 2316 ; CHECK-NEXT: $w0 = COPY [[UBFMWri]]17 ; CHECK-NEXT: RET_ReallyLR implicit $w018 %0:gpr(s32) = COPY $w019 %1:gpr(s32) = G_CONSTANT i32 820 %2:gpr(s32) = G_SHL %0, %1(s32)21 $w0 = COPY %2(s32)22 RET_ReallyLR implicit $w023 24...25---26name: shl_cimm_6427legalized: true28regBankSelected: true29body: |30 bb.1:31 liveins: $x032 33 ; CHECK-LABEL: name: shl_cimm_6434 ; CHECK: liveins: $x035 ; CHECK-NEXT: {{ $}}36 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x037 ; CHECK-NEXT: [[UBFMXri:%[0-9]+]]:gpr64 = UBFMXri [[COPY]], 56, 5538 ; CHECK-NEXT: $x0 = COPY [[UBFMXri]]39 ; CHECK-NEXT: RET_ReallyLR implicit $x040 %0:gpr(s64) = COPY $x041 %1:gpr(s64) = G_CONSTANT i64 842 %2:gpr(s64) = G_SHL %0, %1(s64)43 $x0 = COPY %2(s64)44 RET_ReallyLR implicit $x045 46...47---48name: lshr_cimm_3249legalized: true50regBankSelected: true51body: |52 bb.1:53 liveins: $w054 55 ; CHECK-LABEL: name: lshr_cimm_3256 ; CHECK: liveins: $w057 ; CHECK-NEXT: {{ $}}58 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w059 ; CHECK-NEXT: [[UBFMWri:%[0-9]+]]:gpr32 = UBFMWri [[COPY]], 8, 3160 ; CHECK-NEXT: $w0 = COPY [[UBFMWri]]61 ; CHECK-NEXT: RET_ReallyLR implicit $w062 %0:gpr(s32) = COPY $w063 %3:gpr(s64) = G_CONSTANT i64 864 %2:gpr(s32) = G_LSHR %0, %3(s64)65 $w0 = COPY %2(s32)66 RET_ReallyLR implicit $w067 68...69---70name: lshr_cimm_6471legalized: true72regBankSelected: true73body: |74 bb.1:75 liveins: $x076 77 ; CHECK-LABEL: name: lshr_cimm_6478 ; CHECK: liveins: $x079 ; CHECK-NEXT: {{ $}}80 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x081 ; CHECK-NEXT: [[UBFMXri:%[0-9]+]]:gpr64 = UBFMXri [[COPY]], 8, 6382 ; CHECK-NEXT: $x0 = COPY [[UBFMXri]]83 ; CHECK-NEXT: RET_ReallyLR implicit $x084 %0:gpr(s64) = COPY $x085 %1:gpr(s64) = G_CONSTANT i64 886 %2:gpr(s64) = G_LSHR %0, %1(s64)87 $x0 = COPY %2(s64)88 RET_ReallyLR implicit $x089 90...91---92name: ashr_cimm_3293legalized: true94regBankSelected: true95body: |96 bb.1:97 liveins: $w098 99 ; CHECK-LABEL: name: ashr_cimm_32100 ; CHECK: liveins: $w0101 ; CHECK-NEXT: {{ $}}102 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0103 ; CHECK-NEXT: [[SBFMWri:%[0-9]+]]:gpr32 = SBFMWri [[COPY]], 8, 31104 ; CHECK-NEXT: $w0 = COPY [[SBFMWri]]105 ; CHECK-NEXT: RET_ReallyLR implicit $w0106 %0:gpr(s32) = COPY $w0107 %3:gpr(s64) = G_CONSTANT i64 8108 %2:gpr(s32) = G_ASHR %0, %3(s64)109 $w0 = COPY %2(s32)110 RET_ReallyLR implicit $w0111 112...113---114name: ashr_cimm_32_64115legalized: true116regBankSelected: true117body: |118 bb.1:119 liveins: $w0120 121 ; CHECK-LABEL: name: ashr_cimm_32_64122 ; CHECK: liveins: $w0123 ; CHECK-NEXT: {{ $}}124 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0125 ; CHECK-NEXT: [[MOVi64imm:%[0-9]+]]:gpr64 = MOVi64imm -8126 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY [[MOVi64imm]].sub_32127 ; CHECK-NEXT: [[ASRVWr:%[0-9]+]]:gpr32 = ASRVWr [[COPY]], [[COPY1]]128 ; CHECK-NEXT: $w0 = COPY [[ASRVWr]]129 ; CHECK-NEXT: RET_ReallyLR implicit $w0130 %0:gpr(s32) = COPY $w0131 %3:gpr(s64) = G_CONSTANT i64 -8132 %2:gpr(s32) = G_ASHR %0, %3(s64)133 $w0 = COPY %2(s32)134 RET_ReallyLR implicit $w0135 136...137---138name: lshr_cimm_32_64139legalized: true140regBankSelected: true141body: |142 bb.1:143 liveins: $w0144 145 ; CHECK-LABEL: name: lshr_cimm_32_64146 ; CHECK: liveins: $w0147 ; CHECK-NEXT: {{ $}}148 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0149 ; CHECK-NEXT: [[MOVi64imm:%[0-9]+]]:gpr64 = MOVi64imm -8150 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY [[MOVi64imm]].sub_32151 ; CHECK-NEXT: [[LSRVWr:%[0-9]+]]:gpr32 = LSRVWr [[COPY]], [[COPY1]]152 ; CHECK-NEXT: $w0 = COPY [[LSRVWr]]153 ; CHECK-NEXT: RET_ReallyLR implicit $w0154 %0:gpr(s32) = COPY $w0155 %3:gpr(s64) = G_CONSTANT i64 -8156 %2:gpr(s32) = G_LSHR %0, %3(s64)157 $w0 = COPY %2(s32)158 RET_ReallyLR implicit $w0159 160...161---162name: ashr_cimm_64163legalized: true164regBankSelected: true165body: |166 bb.1:167 liveins: $x0168 169 ; CHECK-LABEL: name: ashr_cimm_64170 ; CHECK: liveins: $x0171 ; CHECK-NEXT: {{ $}}172 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0173 ; CHECK-NEXT: [[SBFMXri:%[0-9]+]]:gpr64 = SBFMXri [[COPY]], 8, 63174 ; CHECK-NEXT: $x0 = COPY [[SBFMXri]]175 ; CHECK-NEXT: RET_ReallyLR implicit $x0176 %0:gpr(s64) = COPY $x0177 %1:gpr(s64) = G_CONSTANT i64 8178 %2:gpr(s64) = G_ASHR %0, %1(s64)179 $x0 = COPY %2(s64)180 RET_ReallyLR implicit $x0181 182...183---184name: lshr_32_notimm64185legalized: true186regBankSelected: true187body: |188 bb.1:189 liveins: $w0190 191 ; CHECK-LABEL: name: lshr_32_notimm64192 ; CHECK: liveins: $w0193 ; CHECK-NEXT: {{ $}}194 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0195 ; CHECK-NEXT: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 8196 ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[MOVi32imm]], %subreg.sub_32197 ; CHECK-NEXT: [[ANDXri:%[0-9]+]]:gpr64common = ANDXri [[SUBREG_TO_REG]], 8000198 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY [[ANDXri]].sub_32199 ; CHECK-NEXT: [[LSRVWr:%[0-9]+]]:gpr32 = LSRVWr [[COPY]], [[COPY1]]200 ; CHECK-NEXT: $w0 = COPY [[LSRVWr]]201 ; CHECK-NEXT: RET_ReallyLR implicit $w0202 %0:gpr(s32) = COPY $w0203 %3:gpr(s64) = G_CONSTANT i64 8204 %4:gpr(s64) = G_AND %3, %3205 %2:gpr(s32) = G_LSHR %0, %4(s64)206 $w0 = COPY %2(s32)207 RET_ReallyLR implicit $w0208 209...210---211name: ashr_32_notimm64212legalized: true213regBankSelected: true214body: |215 bb.1:216 liveins: $w0217 218 ; CHECK-LABEL: name: ashr_32_notimm64219 ; CHECK: liveins: $w0220 ; CHECK-NEXT: {{ $}}221 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0222 ; CHECK-NEXT: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 8223 ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[MOVi32imm]], %subreg.sub_32224 ; CHECK-NEXT: [[ANDXri:%[0-9]+]]:gpr64common = ANDXri [[SUBREG_TO_REG]], 8000225 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY [[ANDXri]].sub_32226 ; CHECK-NEXT: [[ASRVWr:%[0-9]+]]:gpr32 = ASRVWr [[COPY]], [[COPY1]]227 ; CHECK-NEXT: $w0 = COPY [[ASRVWr]]228 ; CHECK-NEXT: RET_ReallyLR implicit $w0229 %0:gpr(s32) = COPY $w0230 %3:gpr(s64) = G_CONSTANT i64 8231 %4:gpr(s64) = G_AND %3, %3232 %2:gpr(s32) = G_ASHR %0, %4(s64)233 $w0 = COPY %2(s32)234 RET_ReallyLR implicit $w0235 236...237